2005 Volume 18 Issue 4 Pages 451-456
Line-edge roughness (LER) & line-width roughness (LWR) poses serious problems for the device performance and CD error budget for sub 100nm design rules. Illumination conditions, pitch, resist formulations, resist process conditions, substrates have shown to be the possible origins of LER. With in the resist formulations, polymer composition, dissolution characteristics of polymer during the development process, acid diffusion influence the roughness of the resulting patterns. ITRS (2003) roadmap requires LWR of 2nm (3 sigma) for 65nm DRAM half-pitch for 2007 year of production. Resist formulation optimization can minimize LER but this can not be achievable simply by the resist formulation modifications as the radius of gyration of polymers itself is in the order of 2-5 nm. It is therefore important to study (1) device performance compromises if the required 2nm is not achieved (2) methods to improve the LER after patterning (litho). As for methods to improve the LER after patterning viability of use of rinse solutions, hard bake, RELACS process and some etch process are reported. Possible origins of LER and some attempts to minimize the LER after patterning such as hard bake and RELACSTM process are discussed.
