抄録
This paper describes an evaluation of a 16 Amplitude-Phase-Shift-Keying (16APSK) direct Radio Frequency (RF) signal processing transceiver designed to make reconfigurable communication equipment smaller and more efficient. An experiment board made for the evaluation mainly comprised Field-Programmable Gate Array (FPGAs) for modulation and demodulation, an A/D converter, and a D/A converter. Evaluation of 750 Mbps and 16APSK confirmed that making the transceiver’s Intermediate Frequency (IF) signal processing part less complex enables device scale to be substantially reduced while keeping performance equal to that obtained with conventional digital communication technology. To reduce the number of conversion steps and obtain our destination frequency in the L band, the modulation portion uses a bandpass filter (BPF) to select an aliasing component with a 1.5 GHz sampling frequency. In the same way, the demodulation portion uses direct under-sampling technology to sample the L-band using a signal with a 1.5GHz sampling frequency. An amplitude equalizer inside the transceiver avoids the bit error rate (BER) degradation caused by linear amplitude distortion at the aliasing frequency range of the sampling frequency response in the L band. As a result we succeeded keeping good performance compared with the IF band loopback test using no conversion.
