IEICE Transactions on Communications
Online ISSN : 1745-1345
Print ISSN : 0916-8516
Regular Section
Time Slot Assignment Algorithms to Upstream Links for Decreasing Transmission Latency in IEEE 802.16j Networks
Go HASEGAWAShinpei TANAKAYoshiaki TANIGUCHIHirotaka NAKANO
Author information
JOURNALS RESTRICTED ACCESS

2012 Volume E95.B Issue 5 Pages 1793-1801

Details
Abstract

In this paper, the authors focus on upstream transmission in TDMA-based IEEE 802.16j and propose two time slot assignment algorithms to decrease end-to-end transmission latency. One of the proposed algorithms assigns time slots considering the hop count from a gateway node, and the other takes the path from the relay node to the gateway node into account. In addition, a restriction in assigning time slots is introduced to reduce the delay at each relay node. The algorithms with the restriction assign later time slots considering the time slot order of links connecting a relay node. The performance of the proposed algorithms is evaluated through simulation experiments from the viewpoints of frame size and end-to-end transmission latency, and it is confirmed that the proposed algorithms achieve small transmission latency regardless of packet generation rate in the network, and decrease the transmission latency by up to 70% compared with the existing algorithm.

Information related to the author
© 2012 The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top