Signed Approximate Adder Tree and Quantization- and Bit-Pruning-Aware Training for Digital Computation-in-Memory

抄録

In this work, an 8-bit signed approximate adder (SAA) and a quantization- and bit-pruning-aware training method (QBAT) are proposed to reduce the substantial area and power consumption caused by adder trees for digital Computation-in-Memory (DCiM). QBAT achieves efficient bit pruning and minimizes the accuracy loss caused by the approximation. The SAA reduces area and power consumption by 20% and power-delay product (PDP) by 36.7%. With QBAT, the proposed design achieves 95.5% and 96.4% inference accuracy for Resnet-18 and Resnet-50 models on the CIFAR-10 dataset.