This review provides a current overview of the fabrication processes for superconducting digital circuits at CRAVITY (clean room for analog and digital superconductivity) at the National Institute of Advanced Industrial Science and Technology (AIST), Japan. CRAVITY routinely fabricates superconducting digital circuits using three types of fabrication processes and supplies several thousand chips to its collaborators each year. Researchers at CRAVITY have focused on improving the controllability and uniformity of device parameters and the reliability, which means reducing defects. These three aspects are important for the correct operation of large-scale digital circuits. The current technologies used at CRAVITY permit ±10% controllability over the critical current density (Jc) of Josephson junctions (JJs) with respect to the design values, while the critical current (Ic) uniformity is within 1σ=2% for JJs with areas exceeding 1.0 μm2 and the defect density is on the order of one defect for every 100,000 JJs.
In order to upgrade the refresh rate about High-Resolution (1280×1024) OLED-on-Silicon (OLEDoS) microdisplay, this paper discusses one compression scan strategy by reducing scan time redundancy. This scan strategy firstly compresses the low-bit gray level scan serial as one unit; second, the scan unit is embedded into the high-bit gray level serial and new scan sequence is generated. Furthermore, micro-display platform is designed to verify the scan strategy performance. The experiment shows that this scan strategy can deal with 144Hz refresh rate, which is obviously faster than the traditional scan strategy.
One of the highest performing single-photon detectors in the visible and near-infrared regions is the superconducting nanostrip photon detector (SNSPD or SSPD), which usually uses NbN or NbTiN as the superconductor. Using other superconductors may significantly improve, for example, the operating temperature and count rate characteristics. This paper briefly reviews the current state of the potential, characteristics, thin film growth, and nanofabrication process of SNSPD using various superconductors.
In this paper, the high-power high-efficiency asymmetric Doherty power amplifiers based on high-voltage GaN HEMT devices with internal input matching for base station applications are proposed and described. For a three-way 1:2 asymmetric Doherty structures, an exceptionally high output power of 1 kW with a peak efficiency of 83% and a linear flat power gain of about 15 dB was achieved in a frequency band of 2.11-2.17 GHz, whereas an output power of 59.5 dBm with a peak efficiency of 78% and linear power gain of 12 dB and an output power of 59.2 dBm with a peak efficiency of 65% and a linear power gain of 13 dB were obtained across 1.8-2.2 GHz. To provide a high-efficiency broadband operation, the concept of inverted Doherty structure is applied and described in detail. By using a high-power broadband inverted Doherty amplifier architecture with a 2×120-W GaN HEMT transistor, a saturated power of greater than 54 dBm, a linear power gain of greater than 13 dB and a drain efficiency of greater than 50% at 7-dB power backoff in a frequency bandwidth of 1.8-2.7 GHz were obtained.
A scheme is proposed for generation of large-amplitude short pulses using a transmission line with regularly spaced series-connected tunnel diodes (TDs). In the case where the loaded TD is unique, it is established that the leading edge of the inputted pulse moves slower than the trailing edge, when the pulse amplitude exceeds the peak voltage of the loaded TD; therefore, the pulse width is autonomously reduced through propagation in the line. In this study, we find that this property is true even when the several series-connected TDs are loaded periodically. By these mechanisms, the TD line succeeds in generating large and short pulses. Herein, we clarify the design criteria of the TD line, together with both numerical and experimental validation.
Copper sulfide nanoparticles were successfully prepared by laser ablation in liquid. CuS powders in deionized water were irradiated with nanosecond-pulsed laser (Nd:YAG, SHG) to prepare nanoparticles. Prepared nanoparticles were investigated by scanning electron microscopy (SEM), dynamic light scattering (DLS) and fluorospectrometer. According to the results of SEM and DLS, the primary and secondary particle size was decreased with the increase in laser fluence of laser ablation in liquid. The ratio of Cu and S of prepared nanoparticles were not changed. The absorbance of prepared copper sulfide nanoparticles in water was increased with the increase in laser fluence.
The Internet of Things (IoT) implicates an infrastructure that creates new value by connecting everything with communication networks, and its construction is rapidly progressing in anticipation of its great potential. Enhancing the security of IoT is an essential requirement for supporting IoT. For ensuring IoT security, it is desirable to create a situation that even a terminal component device with many restrictions in computing power and energy capacity can easily verify other devices and data and communicate securely by the use of public key cryptography. To concretely achieve the big goal of penetrating public key cryptographic technology to most IoT end devices, we elaborated the secure cryptographic unit (SCU) built in a low-end microcontroller chip. The SCU comprises a hardware cryptographic engine and a built-in access controlling functionality consisting of a software gate and hardware gate. This paper describes the outline of our SCU construction technology's research and development and prospects.
In this paper, we describe a post-processing technique having high extraction efficiency (ExE) for de-biasing and de-correlating the random bitstream generated by true random number generators (TRNGs). This research is based on the N-bit von Neumann (VN_N) post-processing method. It improves the ExE of the original von Neumann method close to the Shannon entropy bound by a large N value. However, as the N value increases, the mapping table complexity increases exponentially (2N), which made VN_N unsuitable for low-power TRNGs. To overcome this problem, at the algorithm level, we propose a waiting strategy to achieve high ExE with a small N value. At the architectural level, a Hamming weight mapping-based hierarchical structure is used to reconstruct the large mapping table using smaller tables. The hierarchical structure also decreases the correlation factor in the raw bitstream. To develop a technique with high ExE and low-cost, we designed and fabricated an 8-bit von Neumann with waiting strategy (VN_8W) in a 130-nm CMOS. The maximum ExE of VN_8W is 62.21%, which is 2.49 times larger than the ExE of the original von Neumann. NIST SP 800-22 randomness test results proved the de-biasing and de-correlation abilities of VN_8W. As compared with the state-of-the-art optimized 7-element iterated von Neumann, VN_8W achieved more than 20% energy reduction with higher ExE. At 0.45 V and 1 MHz, VN_8W achieved the minimum energy of 0.18 pJ/bit, which was suitable for sub-pJ low energy TRNGs.
This paper demonstrates 300 GHz terahertz wireless communication using CMOS transmitter (TX) and receiver (RX) modules targeting sixth-generation (6G). To extend communication distance, CMOS modules with WR-3.4 waveguide interface and a high-gain antenna of 40 dBi Cassegrain antenna are designed, achieving 36 Gbps throughput at a 1m communication distance. Besides, in order to support orthogonal frequency-division multiplexing (OFDM), a self-heterodyne architecture is introduced, which effectively cancels the phase noise in multi-carrier modulation. As a proof-of-concept (PoC), the paper successfully demonstrates real-time video transfer at a 10m communication distance using fifth-generation (5G) based OFDM at the 300 GHz frequency band.
In this paper, we propose a design method for a diplexer using a surface acoustic wave (SAW) filter, a multilayer ceramic filter, chip inductors, and chip capacitors. A controllable transmission zero can be created in the stopband by designing matching circuits based on the out-of-band characteristics of the SAW filter using this method. The proposed method can achieve good attenuation performance and a compact size because it does not use an additional resonator for creating the controllable transmission zero and the matching circuits are composed of only five components. A diplexer is designed for 2.4 GHz wireless systems and a global positioning system receiver using the proposed method. It is compact (8.0 mm × 8.0 mm), and the measurement results indicate good attenuation performance with the controllable transmission zero.
We design a silicon gate-all-around junctionless field-effect transistor (JLFET) using a step thickness gate oxide (GOX) by the Sentaurus technology computer-aided design simulation. We demonstrate the different gate-induced drain leakage (GIDL) mechanism of the traditional inversion-mode field-effect transistor (IMFET) and JLFET. The off leakage in the IMFET is dominated by the parasitic bipolar junction transistor effect, whereas in the JLFET it is a result of the volume conduction due to the screening effect of the accumulated holes. With the introduction of a 4 nm thick-second GOX and remaining first GOX thickness of 1 nm, the tunneling generation is reduced at the channel-drain interface, leading to a decrease in the off current of the JLFET. A thicker second GOX has the total gate capacitance of JLFETs, where a 0.3 ps improved intrinsic delay is achieved. This alleviates the capacitive load of the transistor in the circuit applications. Finally, the short-channel effects of the step thickness GOX JLFET were investigated with a total gate length from 40 nm to 6 nm. The results indicate that the step thickness GOX JLFETs perform better on the on/off ratio and drain-induced barrier lowering but exhibit a small degradation on the subthreshold swing and threshold roll-off.
This paper theoretically presents that a terahertz (THz) oscillator using a resonant tunneling diode (RTD) and a rectangular cavity, which has previously been proposed, can radiate high output power by the impedance matching between RTD and load through metal–insulator–metal (MIM) capacitors. Based on an established equivalent-circuit model, an equation for output power has been deduced. By changing MIM capacitors, a matching point can be derived for various sizes of rectangular-cavity resonator. Simulation results show that high output power is possible by long cavity. For example, a high output power of 5 mW is expected at 1 THz.
A new threshold circuit technique is proposed for a vibration sensing circuit that operates at a nanowatt power level. The sensing circuits that use sample-and-hold require a clock signal, and they consume power to generate a signal. In the use of a Schmitt trigger circuit that does not use a clock signal, a sink current flows when thresholding the analog signal output. The requirements for millimeter-sized wireless sensor nodes are an average power on the order of a nanowatt and a signal transition time of less than 1 ms. To meet these requirements, our circuit limits the sink current with a nanoampere-level current source. The chattering caused by current limiting is suppressed by feeding back the change in output voltage to the limiting current. The increase in the signal transition time that is caused by current limiting is reduced by accelerating the discharge of the load capacitance. For a test chip fabricated in the 0.35-μm CMOS process, the proposed threshold circuits operate without chattering and the average powers are 0.7-3 nW. The signal transition times are estimated in a circuit simulation to be 65-97 μs. The proposed circuit has 1/150th the power-delay product with no time interval of the sensing operation under the condition that the time interval is 1s. These results indicate that, the proposed threshold circuits are suitable for vibration sensing in millimeter-sized wireless sensor nodes.
In this study, we conduct guided mode analyses for chalcogenide glass channel waveguides using As2Se3 core and As2S3 lower cladding to determine their single-mode conditions across the astronomical N-band (8 — 12μm). The results reveal that a single-mode operation over the band can be achieved by choosing a suitable core-thickness.
There are enlarged requirements of millimeter-wave beamforming phased-array transceivers and high-order modulation multi-input multi-output (MIMO) transceivers. High-performance integrated RF switches are regarded as one of the most critical components for those transceivers to support signal channel distribution and path redundancy. This paper introduces a CMOS high-isolation and low-loss RF switch with a novel switched parallel LC resonance network. The proposed single-pole double-throw (SPDT) RF switch realizes 68 dB port isolation and 1.0 dB insertion loss with an active area of 0.034mm2. The SPDT RF switch is composed of two series-shunt transistor pairs with body-floating technology and a switched parallel LC network. The network uses a turned-off series transistor to resonate out off-capacitance Coff. The measured output third-order intercept (OIP3) is higher than 21 dBm. The proposed SPDT RF switch maintains return losses of all working ports less than 10 dB from 8 GHz to 20 GHz. The high-performance SPDT RF switch is fabricated in standard 65-nm CMOS technology.
This paper presents a high jitter performance injection-locked clock multiplier (ILCM) using an ultra-low power (ULP) voltage-controlled oscillator (VCO) for IoT application in 65-nm CMOS. The proposed transformer-based VCO achieves low flicker noise corner and sub-100 μW power consumption. Double cross-coupled NMOS transistors sharing the same current provide high transconductance. The network using high-Q factor transformer (TF) provides a large tank impedance to minimize the current requirement. Thanks to the low current bias with a small conduction angle in the ULPVCO design, the proposed TF-based VCO's flicker noise can be suppressed, and a good PN can be achieved in flicker region (1/ƒ3) with sub-100 μW power consumption. Thus, a high figure-of-merit (FoM) can be obtained at both 100 kHz and 1MHz without additional inductor. The proposed VCO achieves phase noise of -94.5/-115.3 dBc/Hz at 100 kHz/1MHz frequency offset with a 97 μW power consumption, which corresponds to a -193/-194 dBc/Hz VCO FoM at 2.62 GHz oscillation frequency. The measurement results show that the 1/ƒ3 corner is below60 kHz over the tuning range from 2.57 GHz to 3.40 GHz. Thanks to the proposed low power VCO, the total ILCM achieves 78 fs RMS jitter while using a high reference clock. A 960 fs RMS jitter can be achieved with a 40MHz common reference and 107 μW corresponding power.
A non-volatile memory (NVM) employing MTJ has a lot of strong points such as read/write performance, best endurance and operating-voltage compatibility with standard CMOS. However, it consumes a lot of energy when writing the data. This becomes an obstacle when applying to battery-operated mobile devices. To solve this problem, we propose an approach to augment the capability of the precision scaling technique for the write operation in NVM. Precision scaling is an approximate computing technique to reduce the bit width of data (i.e. precision) for energy reduction. When writing image data to NVM with the precision scaling, the write energy and the image quality are changed according to the write time and the target bit range. We propose an energy-efficient approximate storing scheme for non-volatile flip-flops and a magnetic random-access memory (MRAM) that allows us to write the data by optimizing the bit positions to split the data and the write time for each bit range. By using the statistical model, we obtained optimal values for the write time and the targeted bit range under the trade-off between the write energy reduction and image quality degradation. Simulation results have demonstrated that by using these optimal values the write energy can be reduced up to 50% while maintaining the acceptable image quality. We also investigated the relationship between the input images and the output image quality when using this approach in detail. In addition, we evaluated the energy benefits when applying our approach to nine types of image processing including linear filters and edge detectors. Results showed that the write energy is reduced by further 12.5% at the maximum.
Reducing power consumption is crucial for edge devices using convolutional neural network (CNN). The zero-skipping approach for CNNs is a processing technique widely known for its relatively low power consumption and high speed. This approach stops multiplication and accumulation (MAC) when the multiplication results of the input data and weight are zero. However, this technique requires large logic circuits with around 5% overhead, and the average rate of MAC stopping is approximately 30%. In this paper, we propose a precise zero-skipping method that uses input data and simple logic circuits to stop multipliers and accumulators precisely. We also propose an active data-skipping method to further reduce power consumption by slightly degrading recognition accuracy. In this method, each multiplier and accumulator are stopped by using small values (e.g., 1, 2) as input. We implemented single shot multibox detector 500 (SSD500) network model on a Xilinx ZU9 and applied our proposed techniques. We verified that operations were stopped at a rate of 49.1%, recognition accuracy was degraded by 0.29%, power consumption was reduced from 9.2 to 4.4 W (-52.3%), and circuit overhead was reduced from 5.1 to 2.7% (-45.9%). The proposed techniques were determined to be effective for lowering the power consumption of CNN-based edge devices such as FPGA.
Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.
Convolutional neural networks (CNNs) have dominated a range of applications, from advanced manufacturing to autonomous cars. For energy cost-efficiency, developing low-power hardware for CNNs is a research trend. Due to the large input size, the first few convolutional layers generally consume most latency and hardware resources on hardware design. To address these challenges, this paper proposes an innovative architecture named SLIT to extract feature maps and reconstruct the first few layers on CNNs. In this reconstruction approach, total multiply-accumulate operations are eliminated on the first layers. We evaluate new topology with MNIST, CIFAR, SVHN, and ImageNet datasets on image classification application. Latency and hardware resources of the inference step are evaluated on the chip ZC7Z020-1CLG484C FPGA with Lenet-5 and VGG schemes. On the Lenet-5 scheme, our architecture reduces 39% of latency and 70% of hardware resources with a 0.456 W power consumption compared to previous works. Even though the VGG models perform with a 10% reduction in hardware resources and latency, we hope our overall results will potentially give a new impetus for future studies to reach a higher optimization on hardware design. Notably, the SLIT architecture efficiently merges with most popular CNNs at a slightly sacrificing accuracy of a factor of 0.27% on MNIST, ranging from 0.5% to 1.5% on CIFAR, approximately 2.2% on ImageNet, and remaining the same on SVHN databases.
This paper proposes a pulse-width modulated (PWM) signaling  to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.
Since most sensor data depend on each other, time-series anomaly detection is one of practical applications of IoT devices. Such tasks are handled by Recurrent Neural Networks (RNNs) with a feedback structure, such as Long Short Term Memory. However, their learning phase based on Stochastic Gradient Descent (SGD) is computationally expensive for such edge devices. This issue is addressed by executing their learning on high-performance server machines, but it introduces a communication overhead and additional power consumption. On the other hand, Recursive Least-Squares Echo State Network (RLSESN) is a simple RNN that can be trained at low cost using the least-squares method rather than SGD. In this paper, we propose its area-efficient hardware implementation for edge devices and adapt it to human activity anomaly detection as an example of interdependent time-series sensor data. The model is implemented in Verilog HDL, synthesized with a 45nm process technology, and evaluated in terms of the anomaly capability, hardware amount, and performance. The evaluation results demonstrate that the RLS-ESN core with a feedback structure is more robust to hyper parameters than an existing Online Sequential Extreme Learning Machine (OS-ELM) core. It consumes only 1.25 times larger hardware amount and 1.11 times longer latency than the existing OS-ELM core.
Recent IoT devices require extremely low standby power consumption, while a certain performance is needed during the active time, and Coarse-Grained Reconfigurable Arrays (CGRAs) have received attention because of their high energy efficiency. For further reduction of the standby energy consumption of CGRAs, the leakage power for their configuration memory must be reduced. Although the power gating is a common technique, the lost data in flip-flops and memory must be retrieved after the wake-up. Recovering everything requires numerous state transitions and considerable overhead both on its execution time and energy. To address the problem, Non-volatile Cool Mega Array (NVCMA), a CGRA providing non-volatile flip-flops (NVFFs) with spin transfer torque type non-volatile memory (NVM) technology has been developed. However, in general, non-volatile memory technologies have problems with reliability. Some NVFFs are stacked-at-0/1, and cannot store the data in a certain possibility. To improve the chip yield, we propose a mapping algorithm to avoid faulty processing elements of the CGRA caused by the erroneous configuration data. Next, we also propose a method to add an error-correcting code (ECC) mechanism to NVFFs for the configuration and constant memory. The proposed method was applied to NVCMA to evaluate the availability rate and reduction of write time. By using both methods, the average availability ratio of 94.2% was achieved, while the average availability ratio of the nine applications was 0.056% when the probability of failure of the FF was 0.01. The energy for storing data becomes about 2.3 times because of the hardware overhead of ECC but the proposed method can save 8.6% of the writing power on average.
IoT devices operate with a battery and have embedded firmware in flash memory. If the embedded firmware is not kept up to date, there is a possibility of problems that cannot be linked with other IoT networks, so it is necessary to maintain the latest firmware with frequent updates. However, because firmware updates require developers and equipment, they consume manpower and time. Additionally, because the device must be active during the update, low-power operation is not possible due to frequent flash memory access. In addition, if an unexpected interruption occurs during an update, the device is unavailable and requires a reliable update. Therefore, this paper aims to improve the reliability of updates and low-power operation by proposing a technique of performing firmware updates at high speed. In this paper, we propose a technique to update only a part of the firmware stored in nonvolatile flash memory without pre-processing to generate delta files. The firmware is divided into function blocks, and their addresses are collectively managed in a separate area called a function map. When updating the firmware, only the new function block to be updated is transmitted from the host downloader, and the bootloader proceeds with the update using the function block stored in the flash memory. Instead of transmitting the entire new firmware and writing it in the memory, using only function block reduces the amount of resources required for updating. Function-blocks can be called indirectly through a function map, so that the update can be completed by modifying only the function map regardless of the physical location. Our evaluation results show that the proposed technique effectively reduces the time cost, energy consumption, and additional memory usage overhead that can occur when updating firmware.
We fabricated silicon nanowires (SiNWs) using a metal-catalyzed electroless etching method, which is known to be a low-cost and simple technique. The SiNW arrays with a length of 540 nm were used as a substrate of SiNWs/PEDOT:PSS hybrid solar cell. Furthermore, gold nanoparticles (AuNPs) were used to improve the light absorption of the device due to localized surface plasmon excitation. The results show that the short-circuit current density and the power conversion efficiency increased from 22.1 mA/cm2 to 26.0 mA/cm2 and 6.91% to 8.56%, respectively. The advantage of a higher interface area between the organic and inorganic semiconductors was established by using SiNW arrays and higher absorption light incorporated with AuNPs for improving the performance of the developed solar cell.
In vacuum-deposited film composed of organic polar molecules, polarization charges appear on the film surface owing to spontaneous orientation of the molecule. Because its density (σpol) determines an amount of accumulation charge (σacc) in organic light-emitting diodes and output power in polar molecular-based vibrational energy generators (VEGs), control of molecular orientation is highly required. Recently, several groups have reported that dipole-dipole interaction between polar molecules induces anti-parallel orientation which does not contribute to σpol. In other words, perturbation inducing the attenuation of the dipole interaction is needed to enhance σpol. In this study, to investigate an effect of light irradiation on σpol, we prepared 1,3,5-tris(1-phenyl-1H-benzimidazol-2-yl)benzene (TPBi) film under illumination during its deposition, and evaluated the σacc in TPBi-based bilayer device, which equals to σpol. We found that the σacc was increased by light irradiation, indicating that average orientation of TPBi is enhanced. These results suggest that light irradiation during device fabrication is promising process for organic electronic devices including polar molecule-based VEGs.
This study proposes a design method for a rectifier circuit that can be rapidly charged by focusing on the design-load value of the circuit and the load fluctuation of a storage capacitor. The design-load value is suitable for rapidly charging the capacitor. It can be obtained at the lowest reflection condition and estimated according to the circuit design. This is a conventional method for designing the rectifier circuit using the optimum load. First, we designed rectifier circuits for the following three cases. The first circuit design uses a load set to 10 kΩ. The second design uses a load of 30 kΩ that is larger than the optimum load. The third design utilizes a load of 3 kΩ. Then, we measure the charging time to design the capacitor on each circuit. Consequently, the results show that the charge time could be shortened by employing the design-load value lower than that used in the conventional design. Finally, we discuss herein whether this design method can be applied regardless of the rectifier circuit topology.
Due to the slowdown of Moore's Law, power limitation has been one of the most critical issues for current and future HPC systems. To more efficiently utilize HPC systems when power budgets or deadlines are given, it is very desirable to accurately estimate the performance or power consumption of applications before conducting their tuned production runs on any specific systems. In order to ease such estimations, we showcase a straight-forward and yet effective method, based on the enhanced power management framework and DSL we developed, to help HPC users to clarify the performance and power relationships of their applications. This method demonstrates an easy process of profiling, modeling and management on both performance and power of HPC systems and applications. In our evaluations, only a few (up to 3) profiled runs are necessary before very precise models of HPC applications can be obtained through this method (and algorithm), which has dramatically improved the efficiency of and lowered the difficulty in utilizing HPC systems under limited power budgets.
Scalability of distributed DNN training can be limited by slowdown of specific processes due to unexpected hardware failures. We propose a dynamic process exclusion technique so that training throughput is maximized. Our evaluation using 32 processes with ResNet-50 shows that our proposed technique avoids slowdown by excluding the slow processes by 12.5% to 50% without accuracy loss.
In this study, we devised a biofuel cell (BFC) by impregnating sheet-like cellulose nanofiber (CNF) with liquid fuel (fructose) and sandwiching it with the electrodes, making the structure simple and compact. CNF was considered as a suitable material for BFC because it is biocompatible, has a large specific surface area, and exhibits excellent properties as a catalyst and an adsorbent. In this BFC device, graphene-coated carbon fiber woven cloth (GCFC) was used as the material for preparing the electrodes, and the amount of enzyme modification on the surface of each electrode was enhanced. Further, as the distance between the electrodes was same as the thickness of the sheet-shaped CNF, it facilitated the exchange of protons between the electrodes. Moreover, the cathode, which requires an oxidation reaction, was exposed to the atmosphere to enhance the oxygen uptake. The maximum power density of the CNF-type BFC was recorded as 114.5 μW/cm2 at a voltage of 293 mV. This is more than 1.5 times higher than that of the liquid-fuel-type BFC. When measured after 24 h, the maximum power density was recorded as 44.9 μW/cm2 at 236 mV, and the output was maintained at 39% of that observed at the beginning of the measurement. However, it is not the case with general BFCs, where the power generation after 24 h is less than 5%. Therefore, the CNF-type BFCs have a longer lifespan and are fuel efficient.
Improvement of output and lifetime is a problem for biofuel cells. A structure was adopted in which gelation mixed with agarose and fuel (fructose) was sandwiched by electrodes made of graphene-coated carbon fiber. The cathode surface not contacting the gel was exposed to air. In addition, the anode surface not contacting the gel was in contact with fuel liquid to prevent the gel from being dry. The power density of the fuel cell was improved by increasing oxygen supply from air and the lifetime was improved by maintaining wet gel, that is, the proposed structure was a hybrid type having advantages of both fuel gel and fuel liquid. The output increased almost up to that of just using fuel gel and did not decrease significantly over time. The maximum power density in the proposed system was approximately 74.0 μW/cm2, an enhancement of approximately 1.5 times that in the case of using liquid fuel. The power density after 24 h was approximately 46.1 μW/cm2, which was 62% of the initial value.
In this study, two modification methods that employ graphene-coated carbon fiber woven fabric (GCFC) as an electrode and 2,2'-azino-bis(3-ethylbenzothiazoline-6-sulfonic acid (ABTS) as a mediator were used to evaluate cathode performance. In addition, a prototype of an atmosphere-exposed ascorbic-acid enzyme biofuel cell (AAEBFC) consisting of an improved GCFC cathode and ABTS was evaluated. No modification was made in the anode region, and only the cathode region was coated with the enzyme of bilirubin oxidase (BOD). As a result of implementing an ABTS-modified cathode in the AAEBFC, an output of 721 μW/cm2 was obtained at 0.189 V. When the gel thickness was changed, an output of 1200 μW/cm2 was obtained at 0.17 V. To the best of our knowledge, this is currently the highest reported output for an AAEBFC fueled by ascorbic acid.
In fields such as medicine and chemistry, methods for transporting microdroplets are currently necessitated, which include the analysis of reagents, mixing, and separation. As microdroplets become finer, their movement becomes difficult to control as a result of surface tension. This has resulted in the use of an excessive amount of reagents. In this study, we evaluated the dynamic characteristics of microdroplets and the excitation force. Microdroplets were dropped onto a tilted glass substrate, and the displacement of the microdroplets was measured while changing the droplet amount, vibration frequency, and vibration direction. Moreover, the behavior of the droplet just before it started to move was observed, and the relationship between the displacement of the minute droplet and the vibration force was compared and examined.
Biofuel cells (BFCs) using graphene-coated carbon fiber cloth electrodes and glucose gel fuel were fabricated and evaluated. A new structure using fuel gel, in which the anode was embedded in gel and the cathode was exposed to the atmosphere, was adopted. Air-exposed biofuel cells using gel have already been reported, however, adhesion between the anode and the gel was improved by the proposed structure. In addition, the enlargement of the gel area prevented its drying. These innovations improved the power density and lifetime of the BFCs. The anode was modified with a glucose oxidase (GOD) enzyme and a mediator (ferrocene) and the cathode was modified with a bilirubin oxidase enzyme. The power density of the proposed structure was 176.4 μW/cm2 at 0.19 V, which was approximately 3.8 times higher than that of BFCs using liquid fuel (45.9 μW/cm2).
Nano crystalline zinc oxide (ZnO) is deposited by room temperature atomic layer deposition (RT-ALD) using dimethylzinc and a plasma excited humidified Ar without thermal treatments. The TEM observation indicated that the deposited ZnO films were crystallized with grain sizes of ∼20 nm on Si in the course of the RT-ALD process. The crystalline ZnO exhibited semiconducting characteristics in a thin film transistor, where the field-effect mobility was recorded at 1.29 × 10-3 cm2/ V⋅s. It is confirmed that the RT deposited ZnO film has an anticorrosion to hot water. The water vapor transmission rate of 8.4 × 10-3 g⋅m-2⋅day-1 was measured from a 20 nm thick ZnO capped 40 nm thick Al2O3 on a polyethylene naphthalate film. In this paper, we discuss the crystallization of ZnO in the RT ALD process and its applicability to flexible electronics.
An efficient approximate computing circuit is developed for polynomial functions through the hybrid of analog and stochastic domains. Different from the ordinary time-based stochastic computing (TBSC), the proposed circuit exploits not only the duty cycle of pulses but also the pulse strength of the analog current to carry information for multiplications. The accumulation of many multiplications is performed by merely collecting the stochastic-current. As the calculation depth increases, the growth of latency (while summations), signal power weakening, and disparity of output signals (while multiplications) are substantially avoidable in contrast to that in the conventional TBSC. Furthermore, the calculation range spreads to bipolar infinite without scaling, theoretically. The proposed multi-domain stochastic computing (MDSC) is designed and simulated in a 0.18 μm CMOS technology by employing a set of current mirrors and an improved scheme of the TBSC circuit based on the Neuron-MOS mechanism. For proof-of-concept, the multiply and accumulate calculations (MACs) are implemented, achieving an average accuracy of 953%. More importantly, the transistor counting, power consumption, and latency decrease to 61%, 554%, and 42% of the state-of-art TBSC circuit, respectively. The robustness against temperature and process variations is also investigated and presented in detail.
Triboelectric generator is attracting much attention as a power source of electronics application. Electromotive force induced by rubbing is a key for triboelectric generator. From dielectric physics point of view, there are two microscopic origins for electromotive force, i.e., electronic charge displacement and dipolar rotation. A new way for evaluating these two origins is an urgent task. We have been developing an optical second-harmonic generation (SHG) technique as a tool for probing charge displacement and dipolar alignment, selectively, by utilizing wavelength dependent response of SHG to the two origins. In this paper, an experimental way that identifies polarity of electronic charge displacement, i.e., positive charge and negative charge, is proposed. Results showed that the use of local oscillator makes it possible to identify the polarity of charges by means of SHG. As an example, positive and negative charge distribution created by rubbing polyimide surface is illustrated.
This paper reports a single dimensional mode based multiplexer / de-multiplexer using the slab waveguide to realize high modes multiplexing and high integration in the non-MIMO (multi-in multi-out) multimode transmission system. A sufficient mode crosstalk of -20 dB was obtained by selecting suitable parameters of the spacing between the connecting positions of each arrayed waveguide Di, the radius slab waveguide R0 and lateral V-parameter.
We previously developed a new terahertz (THz) wave detection method that utilizes the effect of nonlinear optical (NLO) polymers. The new method provided us with a gapless detection, a wide detection bandwidth, and a simpler optical geometry in the THz wave detection. In this paper, polarization dependences in THz wave detection by the Stark effect were investigated. The projection model was employed to analyze the polarization dependences and the consistency with experiments was observed qualitatively, surely supporting the use of the first-order Stark effect in this method. The relations between THz wave detection by the Stark effect and Stark spectroscopy or electroabsorption spectroscopy are also discussed.
A noise-robust and accuracy-enhanced microwave imaging algorithm is presented for microwave ablation monitoring of cancer treatment. The ablation impact of dielectric change can be assessed by microwave inverse scattering analysis, where the dimension and dielectric drop of the ablation zone enable safe ablation monitoring. We focus on the distorted Born iterative method (DBIM), which is applicable to highly heterogeneous and contrasted dielectric profiles. As the reconstruction accuracy and convergence speed of DBIM depend largely on the initial estimate of the dielectric profile or noise level, this study exploits a prior estimate of the DBIM for the pre-ablation state to accelerate the convergence speed and introduces the matched-filter-based noise reduction scheme in the DBIM framework. The two-dimensional finite-difference time-domain numerical test with realistic breast phantoms shows that our method significantly enhances the reconstruction accuracy with a lower computational cost.
It is found that the electrical resistance-length characteristic in an electroactive supercoiled polymer artificial muscle strongly depends on the temperature. This may come from the thermal expansion of coils in the artificial muscle, which increases the contact area of neighboring coils and results in a lower electrical resistance at a higher temperature. On the other hand, the electrical resistance-length characteristic collected during electrical driving seriously deviates from those collected at constant temperatures. Inhomogeneous heating during electrical driving seems to be a key for the deviation.
The optical properties of new tricyanopyrroline (TCP)-based chromophores with a benzyloxy group bound to aminobenzene donor unit were characterized by hyper-Rayleigh scattering (HRS), absorption spectrum, and 1H-NMR measurements, and the influence of the benzyloxy group on TCP-based chromophores was discussed based on the data. A positive effect of NLO properties was found in TCP-based NLO chromophores with a benzyloxy group compared with benchmark NLO chromophores without the benzyloxy group, suggesting an influence of intra-molecular hydrogen bond. Furthermore, we propose a formation of double intra-molecular hydrogen bonds in the TCP chromophore with monoene as the π-conjugation bridge and aminobenzene with a benzyloxy group as the donor unit.
Electromagnetic scattering of an electromagnetic plane wave from a rectangular hole in a thick conducting screen is solved using the Kirchhoff approximation (KA). The scattering fields can be derived as field radiations from equivalent magnetic current sources on the aperture of the hole. Some numerical results are compared with those by the Kobayashi potential (KP) method. The proposed method can be found to be efficient to solve the diffraction problem for high frequency regime.
In this paper, we propose a cross-correlation method applied to multistatic ground penetrating radar (GPR) data sets to detect road pavement damage. Pavement cracks and delamination cause variations in electromagnetic wave propagation. The proposed method can detect velocity change using cross-correlation of data traces at different times. An artificially damaged airport taxiway model was measured, and the method captures the positions of damaged parts.