抄録
Configurable clock is necessary for many applications such as digital communication systems, however, using the conventional direct digital frequency synthesizer (DDS) as a pulse or clock generator may cause jitter problems. People usually employ phase-interpolation approaches to generate a pulse or clock with correct time intervals. This work proposes a new phase-interpolation DDS scheme, which uses the output of the phase accumulator to provide an initial voltage on an integration capacitor by pre-charging in the first phase, and then performs integration operation on the same integration capacitor in the second phase. By using single capacitor integration, the instability of the delay generator existed in the phase-interpolation DDS can be avoided, and the impact caused by capacitance error in the circuit implementation also can be reduced. Furthermore, without ROM tables, the proposed DDS using pre-charging integration not only reduces the spurious level of the clock output, but also has a low hardware complexity.
