抄録
A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20GHz. The fabricated receiver has a maximum conversion gain of 19.4dB, a minimum single-side band noise figure of 10.2dB, the input-referred 1-dB compression point of −20dBm and the input third order inter-modulation intercept point of −8.3dB. It draws only 15.8mA from a 1.2-V power supply with a total chip area of 0.794mm × 0.794mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.
