抄録
In this letter, a novel body bias selection scheme for minimizing the leakage of MOS transistors is presented. The proposed scheme directly monitors leakages at present and adjacent body bias voltages, and dynamically updates the voltage at which the leakage is minimized regardless of process and temperature variations. Comparison results in a 46nm CMOS technology indicated that the proposed scheme achieved leakage reductions of up to 68% as compared to conventional body biasing schemes.
