Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits

Takeshi OKUMOTO; Kumpei YOSHIKAWA; Makoto NAGATA

doi:10.1587/transele.E96.C.538

Special Section on Solid-State Circuit Design—Architecture, Circuit, Device and Design Methodology

Design of Effective Supply Voltage Monitor for Measuring Power Rails of Integrated Circuits

Takeshi OKUMOTO, Kumpei YOSHIKAWA, Makoto NAGATA

著者情報

キーワード: noise detection circuit, power supply noise, power supply integrity, systems-on-a-chip

ジャーナル認証あり

2013 年 E96.C 巻 4 号 p. 538-545

DOI https://doi.org/10.1587/transele.E96.C.538

詳細

抄録

An effective supply voltage monitor evaluates dynamic variation of (V_dd-V_ss) within power rails of integrated circuits on a die. The monitor occupies an area of as small as 10.8×14.5µm² and is followed by backend digitizing circuits, both using 3.3V thick oxide transistors in a 65nm CMOS technology for covering all power domains from core circuits to peripheral I/O rings. A prototype demonstrates capturing of effective supply voltage waveforms in digital (shift registers) as well as in analog (4bit Flash ADC) circuits.

責任著者(Corresponding author)

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