抄録
In this paper, we propose a new design technique called asynchronous multi-frequency clocking for suppressing EMI at a chip design level by combining two independent EMI-suppressing approaches: multi-frequency clocking and asynchronous circuit design techniques. To show the effectiveness of our approach, a five-stage pipelined asynchronous MIPS with multi-frequency clocking has been implemented on a commercial Xilinx FPGA device. Our approach shows 11.05 dB and 5.88 dB reductions of peak EM radiation in the prototyped implementation when compared to conventional synchronous and bundled-data asynchronous circuit counterparts, respectively.
