IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Regular Section
New Address Method for Reducing the Address Power Consumption in AC-PDP
Beong-Ha LIMGun-Su KIMDong-Ho LEEHeung-Sik TAESeok-Hyun LEE
著者情報
ジャーナル 認証あり

2014 年 E97.C 巻 8 号 p. 820-827

詳細
抄録
This paper proposes a new address method to reduce the address power consumption in an AC plasma panel display (AC-PDP). We apply an overlap scan method, in which the scan pulse overlaps with those of the previous scan time and the next scan time. The overlap scan method decreases the address voltage and consequently reduces the address power consumption. However, the drawback of this method is the narrow address voltage margin. This occurs because the maximum address voltage decreases much more than the minimum address voltage does. In order to increase the address voltage margin, we apply a two-step address voltage waveform, in the overlap scan method. In this case, the maximum address voltage increases; however, the minimum address voltage is almost the same. This leads to a wide address voltage margin. Moreover, the two-step address voltage waveform reduces the address power consumption, because the address voltage rises and falls in two steps using an energy recovery capacitor. Consequently, the experimental results show that the new address method reduces the address power consumption by 19.6 Wh (58%) when compared with the conventional method.
著者関連情報
© 2014 The Institute of Electronics, Information and Communication Engineers
前の記事 次の記事
feedback
Top