抄録
In this paper, a 1.8-V 10-bit 100 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) simulated in a TSMC 0.18-μm CMOS process is presented. By applying ten comparators followed by an asynchronous trigger logic, the proposed SAR ADC achieves high speed operation. Compared to the conventional SAR ADC, there is no significant delay in the digital feedback logic in this design. With the sampling rate limited only by the ten delays of the capacitor DAC settling and comparators quantization, the proposed SAR ADC achieves a peak SNDR of 61.2 dB at 100 MS/s and 80 MS/s, consuming 3.2 mW and 3.1 mW respectively.
