IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism
Yuta UKONShimpei SATOAtsushi TAKAHASHI
著者情報
ジャーナル 認証あり 早期公開

論文ID: 2020CDP0007

詳細
抄録

Advanced information-processing services such as computer vision require a high-performance digital circuit to perform high-load processing at high speed. To achieve high-speed processing, several image-processing applications use an approximate computing technique to reduce idle time of the circuit. However, it is difficult to design the high-speed image-processing circuit while controlling the error rate so as not to degrade service quality, and this technique is used for only a few applications. In this paper, we propose a method that achieves high-speed processing effectively in which processing time for each task is changed by roughly detecting its completion. Using this method, a high-speed processing circuit with a low error rate can be designed. The error rate is controllable, and a circuit design method to minimize the error rate is also presented in this paper. To confirm the effectiveness of our proposal, a ripple-carry adder (RCA), 2-dimensional discrete cosine transform (2D-DCT) circuit, and histogram of oriented gradients (HOG) feature calculation circuit are evaluated. Effective clock periods of these circuits obtained by our method with around 1% error rate are improved about 64%, 6%, and 12%, respectively, compared with circuits without error. Furthermore, the impact of the miscalculation on a video monitoring service using an object detection application is investigated. As a result, more than 99% of detection points required to be obtained are detected, and it is confirmed the miscalculation hardly degrades the service quality.

著者関連情報
© 2020 The Institute of Electronics, Information and Communication Engineers
前の記事 次の記事
feedback
Top