IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524

この記事には本公開記事があります。本公開記事を参照してください。
引用する場合も本公開記事を引用してください。

A Feasibility Study of Multi-Domain Stochastic Computing Circuit
Tati ERLINARenyuan ZHANGYasuhiko NAKASHIMA
著者情報
ジャーナル フリー 早期公開

論文ID: 2020ECP5015

この記事には本公開記事があります。
詳細
抄録

An efficient approximate computing circuit is developed for polynomial functions through the hybrid of analog and stochastic domains. Different from the ordinary time-based stochastic computing (TBSC), the proposed circuit exploits not only the duty cycle of pulses but also the pulse strength of the analog current to carry information for multiplications. The accumulation of many multiplications is performed by merely collecting the stochastic-current. As the calculation depth increases, the growth of latency (while summations), signal power weakening, and disparity of output signals (while multiplications) are substantially avoidable in contrast to that in the conventional TBSC. Furthermore, the calculation range spreads to bipolar infinite without scaling, theoretically. The proposed multi-domain stochastic computing (MDSC) is designed and simulated in a 0.18 μm CMOS technology by employing a set of current mirrors and an improved scheme of the TBSC circuit based on the Neuron-MOS mechanism. For proof-of-concept, the multiply and accumulate calculations (MACs) are implemented, achieving an average accuracy of 95•3%. More importantly, the transistor counting, power consumption, and latency decrease to 6•1%, 55•4%, and 4•2% of the state-of-art TBSC circuit, respectively. The robustness against temperature and process variations is also investigated and presented in detail.

著者関連情報
© 2020 The Institute of Electronics, Information and Communication Engineers
feedback
Top