IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Design and Investigation of Silicon Gate-All-Around Junctionless Field-Effect Transistor Using a Step Thickness Gate Oxide
Wenlun ZhangBaokang Wang
著者情報
キーワード: JLFET, TCAD, GIDL, BTBT, GAA Transistor
ジャーナル 認証あり 早期公開

論文ID: 2020ECP5042

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We design a silicon gate-all-around junctionless field-effect transistor (JLFET) using a step thickness gate oxide (GOX) by the Sentaurus technology computer-aided design simulation. We demonstrate the different gate-induced drain leakage (GIDL) mechanism of the traditional inversion-mode field-effect transistor (IMFET) and JLFET. The off leakage in the IMFET is dominated by the parasitic bipolar junction transistor effect, whereas in the JLFET it is a result of the volume conduction due to the screening effect of the accumulated holes. With the introduction of a 4 nm thick-second GOX and remaining first GOX thickness of 1 nm, the tunneling generation is reduced at the channel-drain interface, leading to a decrease in the off current of the JLFET. A thicker second GOX has the total gate capacitance of JLFETs, where a 0.3 ps improved intrinsic delay is achieved. This alleviates the capacitive load of the transistor in the circuit applications. Finally, the short-channel effects of the step thickness GOX JLFET were investigated with a total gate length from 40 nm to 6 nm. The results indicate that the step thickness GOX JLFETs perform better on the on/off ratio and drain-induced barrier lowering but exhibit a small degradation on the subthreshold swing and threshold roll-off.

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© 2021 The Institute of Electronics, Information and Communication Engineers
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