IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524

この記事には本公開記事があります。本公開記事を参照してください。
引用する場合も本公開記事を引用してください。

A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities
Zian CHENTakashi OHSAWA
著者情報
ジャーナル 認証あり 早期公開

論文ID: 2021ECP5040

この記事には本公開記事があります。
詳細
抄録

A new software based in-situ training (SBIST) method to achieve high accuracies is proposed for binarized neural networks inference accelerator chips in which measured offsets in sense amplifiers (activation binarizers) are transformed into biases in the training software. To expedite this individual training, the initial values for the weights are taken from results of a common forming training process which is conducted in advance by using the offset fluctuation distribution averaged over the fabrication line. SPICE simulation inference results for the accelerator predict that the accuracy recovers to higher than 90% even when the amplifier offset is as large as 40mV only after a few epochs of the individual training.

著者関連情報
© 2022 The Institute of Electronics, Information and Communication Engineers
feedback
Top