Design and Implementation of Energy-Efficient Majority-Logic-Based Approximate Adders Using Adiabatic Quantum-Flux-Parametron Technology

抄録

Adiabatic quantum-flux-parametron (AQFP), a superconductor logic system, has the potential to achieve 10⁴-10⁵ times greater energy e!ciency than advanced CMOS while operating at several gigahertz clock frequencies. However, it requires improved circuit density. Approximate computing, a novel computing paradigm, reduces complexity and power consumption at the expense of accuracy, and is aimed at applications that can tolerate certain levels of faults. Hence, employing approximate computing in the design of AQFP arithmetic circuits not only enables further reduction in power consumption but also improves circuit density. In this study, we introduce two 2-bit approximate adders with different architectures, primarily utilizing three-input and five-input majority gates, which are compatible with the existing AQFP standard cell library. Our designs aim to reduce circuit complexity while maintaining a reasonable level of accuracy. The performance of these designs is evaluated based on multiple criteria, including Josephson junction (JJ) counts, circuit delays, energy, and error metrics. Our MAJ35AA design, composed of both a three-input majority gate and a five-input majority gate, shows superior hardware performance. It achieves a reduction of approximately 15% in JJ counts compared to the existing state-of-the-art approximate design. Furthermore, our design achieves a maximum absolute error (MAE) of 1 and a normalized mean error distance (NMED) of 0.0714, indicating that its accuracy level is equivalent to that of the state-of-the-art designs. We fabricated this design using the AIST 10 kA/cm² high-speed standard process (HSTP) and validated its functionality through cryogenic measurements.