Special Section on VLSI Design and CAD Algorithms
Authenticated-Encrypted Analog-to-Digital Conversion Based on Non-Linearity and Redundancy Transformation
2019 年 E102.A 巻 12 号 p. 1731-1740
詳細
2019 年 E102.A 巻 12 号 p. 1731-1740
We have proposed a generic architecture that can integrate the aspects of confidentiality and integrity into the A/D conversion framework. A conceptual account of the development of the proposed architecture is presented. Using the principle of this architecture we have presented a CMOS circuit design to facilitate a fully integrated Authenticated-Encrypted ADC (AE-ADC). We have implemented and demonstrated a partial 8-bit ADC Analog Front End of this proposed circuit in 0.18µm CMOS with an ENOB of 7.64 bits.
