Regular Section
VHDL Design of a SpaceFibre Routing Switch
2019 年 E102.A 巻 5 号 p. 729-731
詳細
2019 年 E102.A 巻 5 号 p. 729-731
The technology advancement of satellite instruments requires increasingly fast interconnection technologies, for which no standardised solution exists. SpaceFibre is the forthcoming protocol promising to overcome the limitation of its predecessor SpaceWire, offering data-rate higher than 1Gbps. However, while several implementations of the SpaceFibre IP already exist, its Network Layer is still at experimental level. This article describes the architecture of an implemented SpaceFibre Routing Switch and provides synthesis results for common FPGAs.
