2024 年 E107.A 巻 1 号 p. 114-118
In a field of biomedical engineering, not only low-pass filters for high frequency elimination but also notch filters for suppressing powerline interference are necessary to process low-frequency biosignals. For integration of low-frequency filters, chip implementation of large capacitances is major difficulty. As methods to enhance capacitances with small chip area, use of capacitance multipliers is effective. This letter describes design consideration of integrated low-frequency low-pass notch filter employing capacitance multipliers. Two main points are presented. Firstly, a new floating capacitance multiplier is proposed. Secondly, a technique to reduce the number of capacitance multipliers is proposed. By this technique, power consumption is reduced. The proposed techniques are applied a 3rd order low-pass notch filter. Simulation results show the effectiveness of the proposed techniques.
