抄録
An injection-locked clock recovery circuit (CRC) with quadrature outputs based on multiplexed oscillator is presented. The CRC can operate at a half-rate speed to provide an adequate locking range with reasonable jitter and power consumption because both clock edges sample the data waveforms. Implemented by 0.18-μm CMOS technique, experimental results demonstrate that it can achieve the phase noise of the recovered clock about -121.55dBc/Hz at 100-kHz offset and -129.58dBc/Hz at 1-MMz offset with ±25MHz lock range, while operating at the input data rate of 1.55Gb/s.
