IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
An Analysis for Fault-Tolerant 3D Processor Arrays Using 1.5-Track Switches
Tadayoshi HORITAYuuji KATOUItsuo TAKANAMI
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ジャーナル 認証あり

2008 年 E91.A 巻 2 号 p. 623-632

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抄録
This paper deals with redundant 3D mesh processor arrays using 1.5-track switches, considering track and switch faults together with processor faults. Four variants are defined based on the distributions of spare PEs, and arrays of three variants have the same PE redundancies among them, but the fabrication-time costs are different. We investigate in detail how the reliability of a total system changes according to the reliabilities of tracks and switches as well as PEs, and show the concrete values of Mt and Ms, when the reliability of array are almost the same even if its variant is changed, and when it is not so, respectively, where Mt and Ms are the ratio of the hardware complexities of a PE and a track, and that of a PE and a contact point of a switch, respectively. Other results which are effective basis for the design of fault-tolerant 3D PE arrays using 1.5-TSs are given.
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© 2008 The Institute of Electronics, Information and Communication Engineers
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