IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Online ISSN : 1745-1337
Print ISSN : 0916-8508
Regular Section
A Low-Complexity and High-Performance 2D Look-Up Table for LDPC Hardware Implementation
Jung-Chieh CHENPo-Hui YANGJenn-Kaie LAINTzu-Wen CHUNG
著者情報
キーワード: LDPC, sum-product algorithm, 2D LUT
ジャーナル 認証あり

2009 年 E92.A 巻 11 号 p. 2941-2944

詳細
抄録
In this paper, we propose a low-complexity, high-efficiency two-dimensional look-up table (2D LUT) for carrying out the sum-product algorithm in the decoding of low-density parity-check (LDPC) codes. Instead of employing adders for the core operation when updating check node messages, in the proposed scheme, the main term and correction factor of the core operation are successfully merged into a compact 2D LUT. Simulation results indicate that the proposed 2D LUT not only attains close-to-optimal bit error rate performance but also enjoys a low complexity advantage that is suitable for hardware implementation.
著者関連情報
© 2009 The Institute of Electronics, Information and Communication Engineers
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