Special Section on VLSI Design and CAD Algorithms
A Flexible Architecture for TURBO and LDPC Codes
2012 年 E95.A 巻 12 号 p. 2392-2395
詳細
2012 年 E95.A 巻 12 号 p. 2392-2395
Turbo codes and LDPC (Low-Density Parity-Check) codes are two of the most powerful error correction codes that can approach Shannon limit in many communication systems. But there are little architecture presented to support both LDPC and Turbo codes, especially by the means of ASIC. This paper have implemented a common architecture that can decode LDPC and Turbo codes, and it is capable of supporting the WiMAX, WiFi, 3GPP-LTE standard on the same hardware. In this paper, we will carefully describe how to share memory and logic devices in different operation mode. The chip is design in a 130nm CMOS technology, and the maximum clock frequency can reach up to 160MHz. The maximum throughput is about 104Mbps@5.5 iteration for Turbo codes and 136Mbps@10iteration for LDPC codes. Comparing to other existing structure, the design speed, area have significant advantage.
