Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators

Yasuhiro TAKEI; Hasitha Muthumala WAIDYASOORIYA; Masanori HARIYAMA; Michitaka KAMEYAMA

doi:10.1587/transfun.E98.A.2658

Regular Section

Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators

Yasuhiro TAKEI, Hasitha Muthumala WAIDYASOORIYA, Masanori HARIYAMA, Michitaka KAMEYAMA

著者情報

キーワード: heterogeneous multicore, FPGA, custom accelerators, reconfigurable architecture

ジャーナル認証あり

2015 年 E98.A 巻 12 号 p. 2658-2669

DOI https://doi.org/10.1587/transfun.E98.A.2658

詳細

抄録

For an FPGA-based heterogeneous multicore platform, we present the design methodology to reduce the total processing time considering data-transfer. The reconfigurability of recent FPGAs with hard CPU cores allows us to realize a single-chip heterogeneous processor optimized for a given application. The major problem in designing such heterogeneous processors is data-transfer between CPU cores and accelerator cores. The total processing time with data-transfers is modeled considering the overlap of computation time and data-transfer time, and optimal design parameters are searched for.

責任著者(Corresponding author)

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