An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology

抄録

An all-digital time-domain ADC, abbreviated as TAD, is presented in this paper. All-digital structure is intrinsically compatible with the scaling of CMOS technology, and can satisfy the great demand of miniaturized and low-voltage sensor interface. The proposed TAD uses an inverter-based Ring-Delay-Line (RDL) to transform the input signal from voltage domain to time domain. The voltage-modulated time information is then digitized by a composite architecture namely “4-Clock-Edge-Shift Construction” (4CKES). TAD features superior voltage sensitivity and 1st-order noise shaping, which can significantly simplify the power-hungry pre-conditioning circuits. Reconfigurable resolution can be easily achieved by applying different sampling rates. A TAD prototype is fabricated in 65nm CMOS, and consumes a small area of 0.016mm². It achieves a voltage resolution of 82.7µV/LSB at 10MS/s and 1.96µV/LSB at 200kS/s in a narrow input range of 0.1Vpp, merely under 0.6V supply. The highest SNR of TAD prototype is 61.36dB in 20kHz bandwidth at 10MS/s. This paper also analyzes the nonideal effects of TAD and discusses the potential solutions. As the principal drawback, nonlinearity of TAD can be compensated by the differential-setup and digital calibration.