論文ID: 2021KEP0006
This brief presents A 16/32 Gb/s dual-mode transmitter including a linearity calibration loop to maintain amplitude linearity of the SST driver. Linearity detection and corresponding master-slave power supply circuits are designed to implement the proposed architecture. The proposed transmitter is manufactured in a 22nm FD-SOI process. The linearity calibration loop reduces the peak INL errors of the transmitter by 50%, and the RLM rises from 92.4% to 98.5% when the transmitter is in PAM4 mode. The chip area of the transmitter is 0.067 mm2, while the proposed linearity enhanced part is 0.05 × 0.02 mm2 and the total power consumption is 64.6mW with a 1.1V power supply. The linearity calibration loop can be detached from the circuit without consuming extra power.
