Performance Enhancement of the LFSR-Based Unpredictable Random Number Generator in Rocket Core

Abstract

Masaoka et al. introduced an unpredictable random number generator (URNG) using a linear feedback shift register (LFSR) embedded within the CPU. Subsequent work by Kamogari and Ichikawa elucidated the LFSR requirements and the minimal essential period to pass the Diehard test. In this study we investigate a Rocket Core with a built-in LFSR, which was designed according to the results of preceding studies. By sampling the lower 32 bits of the 128-bit LFSR, a random number sequence was generated at a rate of 49.4 Mbit/s on a 50-MHz Rocket Core. The derived random sequence passed both the Diehard and NIST tests. Furthermore, we propose to replace an LFSR with a Leap-ahead LFSR, which applies its characteristic polynomial 32 times in a cycle. This improvement results in a significantly greater generation rate of 451 Mbit/s, while maintaining compliance with the Diehard and the NIST tests. The resource overhead of this URNG is negligible compared to the logic scale of the base system (LiteX/Rocket). Considering its low cost, high generation rate, high randomness quality, and ease of use, the proposed design is regarded to be a promising RNG support solution for a wide range of processors.