IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Regular Section
A Multi-Code Compression Scheme for Test Time Reduction of System-on-Chip Designs
Hong-Ming SHIEHJin-Fu LI
Author information

2008 Volume E91.D Issue 10 Pages 2428-2434


With the nano-scale technology, an system-on-chip (SOC) design may consist of many reusable cores from multiple sources. This causes that the complexity of SOC testing is much higher than that of conventional VLSI chip testing. One of the SOC test challenges is the test data reduction. This paper presents a multi-code compression (MCC) technique to reduce the volume of test data and the test application time. A multi-code decompressor for recovering the compressed test data is also proposed. Experimental results show that the MCC scheme can achieve higher compression ratio than single-code compression schemes. The area cost of the proposed multi-code decompressor is small-only about 3498μm2 based on TSMC 0.18μm standard cell technology.

Content from these authors
© 2008 The Institute of Electronics, Information and Communication Engineers
Previous article Next article