IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Regular Section
Area-Time Efficient Modulo 2n-1 Adder Design Using Hybrid Carry Selection
Su-Hon LINMing-Hwa SHEU
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2008 Volume E91.D Issue 2 Pages 361-362

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Abstract
A new Hybrid-Carry-Selection (HCS) approach for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture is simple and applicable for all n values. Based on 180-nm CMOS technology, the HCS-based modulo 2n-1 adder demonstrates its superiority in Area-Time (AT) performance over existing solutions.
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© 2008 The Institute of Electronics, Information and Communication Engineers
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