An Effective Programmable Memory BIST for Embedded Memory

Abstract

This paper proposes a micro-code based Programmable Memory BIST (PMBIST) architecture that can support various kinds of test algorithms. The proposed Non-linear PMBIST (NPMBIST) guarantees high flexibility and high fault coverage using not only March algorithms but also non-linear algorithms such as Walking and Galloping. This NPMBIST has an optimized hardware overhead, since algorithms can be implemented with the minimum bits by the optimized instructions. Finally, various and complex algorithms can be run thanks to its support of multi-loop.