IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Special Section on Multiple-Valued Logic and VLSI Computing
HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
Liang-Bi CHENJiun-Cheng JUChien-Chou WANGIng-Jer HUANG
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2010 Volume E93.D Issue 8 Pages 2100-2108

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Abstract

Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.

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© 2010 The Institute of Electronics, Information and Communication Engineers
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