IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Regular Section
A 1-Cycle 1.25GHz Bufferless Router for 3D Network-on-Chip
Chaochao FENGZhonghai LUAxel JANTSCHMinxuan ZHANG
Author information

2012 Volume E95.D Issue 5 Pages 1519-1522


In this paper, we propose a 1-cycle high-performance 3D bufferless router with a 3-stage permutation network. The proposed router utilizes the 3-stage permutation network instead of the serialized switch allocator and 7×7 crossbar to achieve the frequency of 1.25GHz in TSMC 65nm technology. Compared with the other two 3D bufferless routers, the proposed router occupies less area and consumes less power consumption. Simulation results under both synthetic and application workloads illustrate that the proposed router achieves less average packet latency than the other two 3D bufferless routers.

Information related to the author
© 2012 The Institute of Electronics, Information and Communication Engineers
Previous article Next article