IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Special Section on Reconfigurable Systems
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design
Yoshiya KOMATSUMasanori HARIYAMAMichitaka KAMEYAMA
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2013 Volume E96.D Issue 8 Pages 1632-1644

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Abstract

This paper presents a novel architecture of an asynchronous FPGA for handshake-component-based design. The handshake-component-based design is suitable for large-scale, complex asynchronous circuit because of its understandability. This paper proposes an area-efficient architecture of an FPGA that is suitable for handshake-component-based asynchronous circuit. Moreover, the Four-Phase Dual-Rail encoding is employed to construct circuits robust to delay variation because the data paths are programmable in FPGA. The FPGA based on the proposed architecture is implemented in a 65nm process. Its evaluation results show that the proposed FPGA can implement handshake components efficiently.

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© 2013 The Institute of Electronics, Information and Communication Engineers
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