IEICE Transactions on Information and Systems
Online ISSN : 1745-1361
Print ISSN : 0916-8532
Special Section on Multiple-Valued Logic and VLSI Computing
A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits
Takashi HIRAYAMAHayato SUGAWARAKatsuhisa YAMANAKAYasuaki NISHITANI
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2014 Volume E97.D Issue 9 Pages 2253-2261

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Abstract
We present a new lower bound on the number of gates in reversible logic circuits that represent a given reversible logic function, in which the circuits are assumed to consist of general Toffoli gates and have no redundant input/output lines. We make a theoretical comparison of lower bounds, and prove that the proposed bound is better than the previous one. Moreover, experimental results for lower bounds on randomly-generated reversible logic functions and reversible benchmarks are given. The results also demonstrate that the proposed lower bound is better than the former one.
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© 2014 The Institute of Electronics, Information and Communication Engineers
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