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Article type: Cover
Pages
Cover1-
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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Article type: Appendix
Pages
App1-
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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Article type: Index
Pages
Toc1-
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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Article type: Appendix
Pages
App2-
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese]
Article type: Article
Pages
1-4
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese], [in Japanese], [in Japanese]
Article type: Article
Pages
5-8
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese]
Article type: Article
Pages
9-12
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese]
Article type: Article
Pages
13-16
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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Ziyuan LIU, Shinji FUJIEDA, Koichi TERASHIMA
Article type: Article
Pages
17-20
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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It was confirmed that negative-bias-temperature stress (NBTS) produces interface states and a post-oxidation annealing (POA) suppresses the interface state production. Hydrogen accumulation to the SiO_2/Si interface is clearly shown to influence the stability of LSI's devices against NBTS.
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[in Japanese], [in Japanese], [in Japanese]
Article type: Article
Pages
21-24
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese]
Article type: Article
Pages
25-28
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese]
Article type: Article
Pages
29-32
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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Masaru SANADA, Kazuo UEHIRA
Article type: Article
Pages
33-36
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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For fault element diagnosis in cell circuits, two diagnosis techniques have been developed using I_<DDQ>. One is a detection way of shorted pairs in transistor elements. This technique is the way to prepare logic state of six pairs, formed by transistor structure, using the logic applied to transistor terminal. Another is a detection way of shorted line pairs in cell circuit. Transistor is defined to logical element and treats as SPICE data. This operation makes it possible to execute the logic simulation of elements in cell. These data combined with layout information are applied to narrow the shorted pairs down.
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[in Japanese]
Article type: Article
Pages
37-40
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese]
Article type: Article
Pages
41-44
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese], [in Japanese], [in Japanese]
Article type: Article
Pages
45-48
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese], [in Japanese]
Article type: Article
Pages
49-52
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese], [in Japanese]
Article type: Article
Pages
53-56
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese], [in Japanese], [in Japanese]
Article type: Article
Pages
57-60
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese], [in Japanese]
Article type: Article
Pages
61-64
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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[in Japanese], [in Japanese], [in Japanese], [in Japanese], [in Japane ...
Article type: Article
Pages
65-68
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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Article type: Cover
Pages
Cover2-
Published: October 24, 2003
Released on J-STAGE: January 31, 2018
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