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  • Suguru YOSHIMIZU, Hiroyuki KOGA, Katsushi KOUYAMA, Masayoshi SHIMAMURA, Kazumi KUMAZOE, Masato TSURU
    IEICE Transactions on Communications
    2010年 E93.B 巻 5 号 1104-1112
    発行日: 2010/05/01
    公開日: 2010/05/01
    ジャーナル 認証あり
    With the emergence of bandwidth-greedy application services, high-speed transport protocols are expected to effectively and aggressively use large amounts of bandwidth in current broadband and multimedia networks. However, when high-speed transport protocols compete with other standard TCP flows, they can occupy most of the available bandwidth leading to disruption of service. To deploy high-speed transport protocols on the Internet, such unfair situations must be improved. In this paper, therefore, we propose a method to improve fairness, called Kyushu-TCP (KTCP), which introduces a non-aggressive period in the congestion avoidance phase to give other standard TCP flows more chances of increasing their transmission rates. This method improves fairness in terms of the throughput by estimating the stably available bandwidth-delay product and adjusting its transmission rate based on this estimation. We show the effectiveness of the proposed method through simulations.
  • Ning Zhang, Ke Wang, Kai Huang
    IEICE Electronics Express
    2024年 21 巻 3 号 20230555
    発行日: 2024/02/10
    公開日: 2024/02/10
    [早期公開] 公開日: 2023/12/28
    ジャーナル フリー

    Logic locking is an efficient defense against attacks to the intellectual property of integrated circuits. However, in recent years, boolean satisfaction based attack (SAT attack) and a structural based attack named Valkyrie were proposed. As far as we know, most of the locking methods failed to achieve security for both of them and keep an acceptable overhead. In this paper, we present a self-adaptive striped-function logic locking method named SFLL-AD, based on repeatedly modifying the structure of the encryption block to a form that: (1) permits splitting and dispersing the encryption block across the netlist to have resilience to Valkryie (2) and guarantees not losing SAT resilience. Experimental results of our mehtod confirm the security to both attacks and show a small overhead (about 10% on average).

  • Jihu Liang, Ke Wang, Wei Xi, Changbao Xu, Junjian Chen, Kai Huang
    IEICE Electronics Express
    2023年 20 巻 2 号 20220512
    発行日: 2023/01/25
    公開日: 2023/01/25
    [早期公開] 公開日: 2022/12/16
    ジャーナル フリー

    Logic locking is an integrated circuits (ICs) protection technique that thwarts reverse engineering, IC overproduction, and IP piracy caused by untrusted foundry and end-users. After Boolean Satisfiability (SAT) solver was applied to crack the keys, researchers proposed various defenses against SAT, approximate, and removal attacks. The Valkyrie attack based on structural analysis has been recently presented that breaks all the existing combinational logic locking techniques. In this letter, we present Structural Interference Logic Locking (SILL) technique. SILL adds interference logic combined with traditional cryptographic logic to drive the primary output, which enables defense against structural attacks by assigning keys to the cryptographic and interference logic according to rules. According to the experimental results, SILL is between (k-4)-secure and (k-2)-secure against SAT Attack while defending against Valkyrie attack.

  • 義江 龍一郎, 飯塚 悟, 伊藤 靖晃, 大岡 龍三, 大風 翼, 大場 正昭, 片岡 浩人, 勝地 弘, 勝村 章, 喜々津 仁密, 白土 博通, 曹 曙陽, 高森 浩治, 田中 英之, 田村 哲郎, 富永 禎秀, 野田 稔, 長谷部 寛, ファム バン フック, 松井 正宏, 松宮 央登, 丸山 敬, 持田 灯, 山口 敦, 吉田 昭仁, 吉田 伸治
    日本風工学会誌
    2011年 36 巻 4 号 406-428
    発行日: 2011年
    公開日: 2012/08/31
    ジャーナル フリー
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