Reconfigurable Computing (RC) has been proposed as a new paradigm to address the conflicting design requirements of high performance and area efficiency. Coarse-grained architecture RC (CGA-RC) operates at the word level of granularity and exhibits better power and performance features than fine-grained architectures. However, in a CGA-RC system, the processing elements (PE) implement several types of multiple arithmetic operations and the routing between them has a fixed architecture. To achieve both good performance and high PE utilization for all applications, we propose PE based pipeline design method, apply it to JPEG encoder, and evaluate its performance.
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