抄録
A stochastic flash analog-to-digital converter (SF-ADC) utilizing device mismatch is designed using a 65-nm CMOS process. Since the proposed SF-ADC uses thresholds determined by the input-referred comparator offsets, the large input-referred offsets are allowed. The quantization error and non-linearity of SF-ADC are demonstrated, and the input range is enlarged by using non-linearity reduction technique. At 1.6GS/s sampling, the designed ADC achieves 34.7dB SFDR and 29.0dB SNDR without any calibration circuits despite the large input-referred offset of 102mV. At this conversion speed, it consumes 134mW with a 1.2-V power supply.
