The Formation of High-Step-Coverage Lateral Interconnection Extending overChips

Abstract

A hetero-integrated packaging (HiP) technology was known as a promising method to fabricate metal interconnections between various functional devices and chips. However, the troublesome caused by high height differences need to be solved, such as different depth-of-fields in photolithography and low coverage of each layer on chip lateral side. In the present work, the processes of semiconductor photolithography and the formation of each layer over a large step height (100mm) was carried out. The electrical properties of fabricated lateral interconnections were measured.