Proceedings of JIEP Annual Meeting
The 22th JIEP Annual Meeting
Session ID : 17C-05
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Proposal of Low Cost Packaging Process
*Kouichi MeguroJunji TanakaMasanori OnoderaJunichi Kasai
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Keywords: BGA, Mold, Warpage
CONFERENCE PROCEEDINGS FREE ACCESS

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Abstract
Regarding the cost of semiconductro package, the substrate cost holds a big ratio. Therefore, to reduce the substrate cost, we developed the packaging process with using big area substrate. At this article, to realize the packaging process, we suggest the new mold method (VDCM: Vacuum Dip Compression Molding) and the method for the warpage reduction that is hard to depend on mold resin and structure of the product.
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© 2008 by The Japan Institute of Electronics Packaging
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