IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Design methodology for determining the number of stages in a cascaded time amplifier to minimize area consumption
Kiichi NiitsuNaohiro HarigaiHaruo Kobayashi
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JOURNALS FREE ACCESS

2013 Volume 10 Issue 11 Pages 20130289

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Abstract

This paper describes a design methodology for determining the number of stages in a cascaded time amplifier to minimize the area consumption. The total area consumption is categorized into three parts, which allows mathematical analysis and optimization to be performed. A combination of the proposed mathematical analysis and 2D mapping can determine the number of stages to minimize the area consumption.

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© 2013 by The Institute of Electronics, Information and Communication Engineers
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