In this express, we propose an improved architecture for modulo (2n+3) multiplication on the condition n≥6. With this architecture, we can design the fastest among all known modulo (2n+3) multipliers. The proposed modulo (2n+3) multiplier can improve the state-of-art by 3.2% on the average in terms of area and 10.1% on the average in terms of performance delay.
