抄録
This paper presents a fully parallelized and scalable RNS Montgomery multiplier over binary field. By generalizing the RNS Montgomery Multiplication (RNS MM) and elaborating a highly efficient RNS base selection, we are able to obtain a considerably high speed in our FPGA implementation experiments with acceptable circuit area and modest critical path delay. Furthermore, this design can be easily scalable by adjusting a variety of field sizes and field polynomials.
