The rapid advancement of power electronics has driven a transition toward more efficient semiconductor devices, with SiC MOSFETs gaining popularity in the 1 kV range for their fast switching and potential to enhance converter power density. While Si and IGBTs continue to dominate many applications, replacing them with SiC devices can substantially improve operating frequency and overall system performance. SiC MOSFETs, however, require specialized gate-driver design because drivers designed for Si devices do not meet the stringent switching, isolation, and biasing requirements of SiC technology. This paper introduces an isolated gate-driver solution specifically designed for SiC MOSFETs and assesses its performance in a bidirectional synchronous H6 inverter. Experimental results show that the proposed gate driver circuitry can reduce SiC switching losses by approximately 15–20% compared with traditional gate driver schemes. As a result, the overall efficiency of the SiC based synchronous H6 inverter increases by up to 2.6% under the tested operating conditions. The enhanced performance of the SiC gate driver comes from reduced switching losses, thereby increasing the overall efficiency of the high-frequency synchronous H6 inverter.

Imperfect fabrication induces capacitor-mismatches that significantly affect the linearity of the successive-approximation-register (SAR) analog-to-digital converter (ADC), leading to significant yield loss. A number of attempts to calibrate the linearity of the SAR ADCs are suffering from the following remarkable limitations: (1) the search resolution for the calibration process restrained by practical (or limited) calibration process time, and (2) the training set with low correlation to the validation set for the machine-learning-driven calibration approaches. To overcome those issues, this paper proposes a machine-learning-based built-in self-calibration scheme for split-SAR ADCs in a system-on-a-chip (SoC). For the configuration, the split-SAR ADC in a SoC is connected with an external digital-to-analog converter (DAC) on the load board for calibration purpose. Two parallel sub-ADCs in the ADC include their capacitive DACs whose binary-weighted capacitor-arrays consist of variable capacitors. The optimal signatures for this work are devised by differently exploiting our previous work, where the previous work calibrates the split-SAR ADC by effectively comparing the binary-weighted capacitors in the ADC. Based on this, this work is performed in the two steps. Firstly, the training process is conducted by generating the efficient two signatures and the two reference values. The first signature is the input control voltages (called input signature) for the variable capacitors of the training set, which are determined by the process restrained by practically limited process time. The second signature is the harmonics (called output signature) of the training set (with the input control voltages obtained above set) by using a DAC on the load board and on-chip digital-signal-processor (DSP) core available in an SoC. The reference values are another set of the input/output signatures which is even more accurately measured during sufficiently long time. Then, the MARS generates the strongly correlated mapping functions among the input/output signatures and their reference values using an on-chip DSP core. Secondly, for the validation process, the input/output signatures are measured from the validation set as in the training process. Those signatures are then applied to the obtained mapping functions to predict the accurate input control voltages for the variable capacitors. Therefore, the ADC linearity can be significantly enhanced based on the proposed self-calibration. The simulation results verified that the total-harmonic-distortion and the signal-to-noise-and-distortion ratio were enhanced from 44-dB to 49-dB and from 43-dB to 48-dB, respectively.

This paper proposes a universal design method for optimizing the winding structure of high-frequency planar transformers to minimize losses and leakage inductance. Unlike traditional approaches that rely on empirical trials and iterative simulations, the proposed method establishes a quantitative relationship model between the winding layer arrangement and the magnetic field distribution. This model provides a systematic and data-driven framework to determine the optimal winding stack-up for both single-layer and multi-layer parallel configurations, thereby addressing the inefficiency and blindness of conventional design processes. The core contribution of this work is the generalized methodology itself. To validate its effectiveness, the method is applied to design transformers with turn ratios of 3:2 and 7:2. Finite element simulations using Ansys Maxwell demonstrate that the optimized winding structures significantly reduce leakage inductance and losses compared to non-optimal arrangements. Furthermore, experimental results from an isolated DC/DC converter prototype show that the transformer designed with the proposed method achieves a notable improvement in output efficiency, confirming the practical value of the universal design method for enhancing the performance of high-frequency power converters.

To address the thermal bottlenecks and noise risks of a compact dual-rotor permanent-magnet-assisted synchronous reluctance motor (PMa-SynRM), this study proposes a reproducible ventilation design and a multiphysics evaluation framework. Leveraging the flux-barrier geometry, a composite ventilation path with axial intake and radial exhaust is configured, taking end-plate inlet-hole diameter and stator ventilation hole number as design variables. Electromagnetic losses are mapped as volumetric heat sources for conjugate heat-transfer simulations, and stator normal surface acceleration from harmonic response is used for acoustic analysis. Results show the optimized ventilation reduces local hot-spot temperatures and overall radiated sound level, achieving coordinated thermal and acoustic improvement.

While eXtended Reality (XR) systems offer immersive see-through experiences, the scarcity of 3D content remains a critical bottleneck. Neural Light Fields (NeLF), an Implicit Neural Representation (INR) approach, presents a promising solution for free-viewpoint rendering. However, traditional NeLF requires computing Multi-Layer Perceptron (MLP) predictions for all light rays, causing prohibitive latency that prevents real-time deployment on resource-constrained standalone XR devices. To address this, we propose an accelerated NeLF framework designed to significantly reduce rendering latency. Specifically, we optimize the Explicit Voxel Grid (EVG) architecture and MLP dimensions to drastically alleviate the computational burden. Furthermore, we introduce a background masking technique that effectively reduces computational overhead by bypassing MLP inferences for non-foreground rays. By combining EVG optimization with this foreground-centric rendering, our method achieves frame rates of approximately 15 to 30 FPS on the Meta Quest 3, successfully enabling interactive free-viewpoint rendering for practical see-through XR applications.