A compact and wide-stopband filtering power divider (FPD) based on a single shielded circular patch resonator (SCPR) is presented in this paper. The SCPR is first introduced, which consists of a circular patch resonator loaded with a center metal via and a ring of shielding metal vias. When the TM₀₀ mode resonates, the half-mode SCPR (HMSCPR) and the quarter-mode SCPR (QMSCPR) obtained by dividing the full-mode SCPR (FMSCPR) with multiple slots have the same resonant frequency. Notedly, as the size of the resonator decreases, some higher-order modes are correspondingly suppressed. By combining an HMSCPR and two QMSCPRs, a compact second-order FPD with improved stopband performance can be realized. The good isolation between output ports can be achieved by loading three isolation resistors at the slots of two adjacent QMSCPRs. A prototype is designed, simulated, and measured to verify the proposed method.

Approximate computing stands as a highly promising approach in curbing power consumption and enhancing energy efficiency in error-tolerant applications, such as image processing and neural networks. This brief introduces two unsigned approximate multiplier designs: MUL1, tailored for high-precision applications, and MUL2, optimized for low-power usage. Furthermore, we propose Approximate N-4 compressors, which are devised based on input reordering circuits, along with a novel approximate 4-2 compressor that align positive and negative approximations for input patterns sharing the same probability. These proposed approximate multipliers have been synthesized using 40nm technology, demonstrating remarkable improvements. In comparison to the exact multiplier, the first proposed multiplier boasts an 84.98% enhancement in the power-delay-area product (PDAP), while the second multiplier achieves an even more significant improvement of 97.22% in this parameter.

A Cascaded hybrid Fibonacci DC-DC converter with interleaved clock for DC grid is proposed. A hybrid Fibonacci stage is connected in series and the interleaved clock is applied. The modified converter is proposed by using two inductors in place of two switches of a typical X3 Fibonacci converter. By this modification, the converter achieved up to 20 of conversion rate (CR) at duty ratio of D=0.84. The converter consists of two switches, three diodes, and three capacitors for a total of 10 elements. This component count is less than that of the past leading works of the high step-up DC-DC converters. The operation principle was verified using PSIM simulator. A laboratory prototype DC-DC converter achieved CR of 19.5 at D=0.85.

This paper presents a hardware-efficient delay ergodic cellular automaton gene-protein network model. It is shown that the presented model can reproduce the occurrence mechanism of one of the most typical nonlinear phenomena (supercritical Hopf bifurcation) of a mathematical gene-protein network model. Then the model is implemented by a field programmable gate array and experiments validate its operations. Furthermore, it is shown that the presented model is much more hardware-efficient compared to DSP-based and CPU-based gene-protein network models. It is then discussed that the presented model will be useful as a building block of a large-scale genome simulator for personalized medicine and drug discovery.

In this paper, an unconventional temperature sensor for harsh environments is proposed, which can be used for real-time measurement of temperature parameters in harsh environments such as high temperature and high pressure by embedding a complementary split resonant ring (CSRR) structure into a substrate integrated waveguide (SIW) structure. After experimental verification, the temperature sensitivity of the sensor is up to 401.2kHz/°C, and the quality factor is still up to 2728.6 at 850°C, which effectively solves the problem of weakening or even annihilating the characteristic signals of wireless sensors at high temperatures. The sensor has the advantages of small size, high structural strength and high temperature corrosion resistance.

True random number generator (TRNG) is the important hardware security primitive for modern internet of things (IoT) devices, while the entropy source (ES) serves as the most crucial component for TRNG. This paper explores the NAND-XOR ring oscillators (NXROs) structure to design a novel ES architecture for TRNG. The basic principle of the ES is to add a self-feedback NAND gate in XOR RO to generate a high-frequency signal, so as to apply the signal to induce a high-frequency change of XOR RO oscillation states and thus to achieve a more significant amplification for random clock jitter. In addition, our NXRO has a higher oscillation frequency and min-entropy than traditional ROs. We implement a TRNG with the new NXRO ES unit on both Xilinx Spartan-6 and Atrix-7 FPGAs. Our experiment results demonstrate that compared with the state-of-the-art TRNGs, the new TRNG achieves a higher throughput and lower hardware overhead in generating true random numbers successfully passing the NIST test and AIS31 test without post-processing.

A novel dual-band high-gain shared-aperture antenna with a large frequency ratio is proposed in this letter. This antenna consists of two layers. Based on the different electromagnetic characteristics at two bands, these two layers can be used to form an Fabry-Perot cavity antenna (FPCA) in the microwave band and an folded transmitarray (FTA) in the millimeter-wave band. By integrating the FPCA into the FTA, we achieve a large frequency ratio of 8.6. A novel feed configuration with a horn in the center and a patch array along the edge is designed. Through the feed configuration based on FPCA and FTA, our shared-aperture antenna achieves higher aperture efficiency at dual bands compared with other similar works. An antenna prototype operating at both 3.5GHz and 30GHz bands is designed, fabricated and measured. Measurements show that the peak realized gain is 11.9dBi at 3.5GHz and 26.2dBi at 30GHz, respectively. The aperture efficiency can reach to 82% at the S band and 30% at the Ka band.

Beat-frequency ADCs emerged as a good choice for applications where low power consumption is important. However, there is a tradeoff between circuit power/area and quantization resolution. An Internal-states Beat-frequency ADC with subcircuit sharing is proposed to improve resolution while reducing the tradeoff. It was observed that SNDR/ENOB were improved by an average of 6.72dB/1.14 bits by using the internal-states analysis without increasing system-wide area/power by means of the subcircuit sharing design method, thus alleviating the previously existing tradeoff.

This letter proposes a spring pendulum piezoelectric and electromagnetic vibration energy harvesting (SP-PEVEH) system. The SP-PEVEH system consists of a spring pendulum harvester and an interface circuit. The spring pendulum harvester can simultaneously generate energy through piezoelectric and magneto-electric transducers. Additionally, the spring pendulum harvester has the capability to harvest multidirectional vibration energy. The interface circuit can transfer energy from the harvesters to the storage. The maximum power point tracking (MPPT) control is also implemented to achieve efficient energy conversion. The experimental results reveal that with a resonant frequency vibration of 26.4Hz and a maximum 1.5m/s² acceleration, the SP-PEVEH system can generate 11.63mW power. As compared with a conventional interface circuit without MPPT control, the output power is increased by 676%.