This paper presents a 5-bit CMOS phase shifter integrating tunable active inductors to achieve compact size, wideband operation, and low phase error. Conventional inductors occupy large silicon area with low quality-factor. To overcome this, a G_m-boosted gyrator-C active inductor with resistive-feedback is used, operating up to 4.1 GHz. The design offers wide inductance tuning from 1.8 nH to 220 nH, improved quality factor, and reduced die area. The phase shifter operates between 2.2-3.6 GHz, with reflection coefficients below -10 dB, an RMS phase error below 3.3°, average insertion loss of 14 dB, and occupies an area of only 0.17 mm², making it ideal for compact phased arrays in radar and 5G systems.

Multi-view stereo (MVS) 3D reconstruction is a fundamental task in computer vision, aiming to recover accurate scene geometry from multi-view images. However, existing methods continue to confront formidable challenges when handling complex scenes. To effectively address the above issues, this paper introduces an improved multi-view stereo-matching framework, AC-GoMVS. To mitigate the susceptibility of standard convolutions to depth noise at occlusion boundaries, we introduce an Adaptive Geometry-aware 3D Convolution (Agp-Conv3D) that exploits a dual-stream architecture comprising a principal pathway and a residual pathway. Furthermore, a dynamic attention mechanism is incorporated into the main path to adaptively adjust sampling positions of depth hypotheses, significantly improving edge detail reconstruction. In addition, a channel attention mechanism is embedded within the geometry consistency aggregation module to dynamically recalibrate the weight distribution of multi-level geometric features, addressing the feature mismatch issue caused by fixed-weight kernels in traditional 3D convolutions. Simultaneously, skip connections and residual links interlaced between the downsampling and upsampling pathways not only preserve rich fine-grained information, but also markedly enhance feature diversity. We evaluated our method on the DTU dataset and the Tanks and Temples benchmark. Experimental results show that, compared with the baseline model, the proposed approach achieves better reconstruction quality and stronger generalization ability.

The variation of oscillator amplitude in inductive position sensors causes a change of noise level on receiving coils, restricting the feasibility of off-line calibration. A method of piece-wise-linear amplitude regulation, realized by adjusting a 7-bit control word n<6:0>, is proposed for oscillators with a wide-range tail current. The n<6:0> is divided into 6 segments, and tail current is made to change exponentially with n<6:0> from segment to segment. This ensures a constant relative amplitude step across all segments, enabling both fast and accurate amplitude regulation. An oscillator with tail current ranged from 0.168 mA to 10.4 mA was designed in a 0.18 μm CMOS process. Simulation results show the maximum amplitude variation at all segments is no more than 70 mV and settling time is the duration of n<6:0>’s monotonic transition from its initial to its final value, in which the affection of amplitude variation upon position accuracy is negligible.

Capacitive power transfer (CPT) do not produce eddy current effects and are concentrated between plates. To increase the capacitance of CPT coupler and satisfy the charging demands of loads, a novel coupler and its associated compensation network are proposed. The coupler elevate the equivalent capacitance to nanofarad-scale. The compensation network designed in this paper can achieve input zero phase angle (ZPA) and load-independent constant-voltage (CV) output. Experimental results demonstrate that the designed coupler’s equivalent capacitance is several times greater than that of traditional structures. The compensation network successfully meets the requirements for input ZPA, CV output, and anti-misalignment performance.

This paper proposes a low-offset balanced inverter that forms a push-pull structure using two composite transistors. Each composite transistor operates as either a current-sourcing or a current-sinking device, and can replace both the PMOS and NMOS transistors in a CMOS inverter. The symmetry between the pull-up and pull-down paths achieves a very low offset, enabling the implementation of a single-ended, lossless integrator without requiring any offset cancellation. The proposed balanced inverter is applied to realize a second-order delta-sigma ADC that digitizes the integration of extremely weak input currents from the resistor. Experimental results from the fabricated chip demonstrate that the resistor measuring ADC achieved a 0.4-Ω resolution over 106-dB dynamic range, confirming its practical applicability despite the process and temperature variations.