To prolong the service life of Li-battery, a traditional charging profile including a constant current (CC) charging first and then constant voltage (CV) charging is widely used. However, current CC/CV conversion methods face several challenges, including precise battery state monitoring, reliable wireless communication, or unavoidable cross-coupling issues. To address these issues, this paper proposes a novel wireless charger topology that enables a smooth transition from CC to CV mode without additional components addition or closed-loop control. A primary CLC compensation network is used to ensure the primary receiving current to be constant. Two parallel loops charge the battery together initially and CC output is realized. As the charging progresses, one branch will be cut off owing to the conduction characteristics of diode and constant voltage output can be realized for CV mode. Finally, an experimental platform with 2.6 A/105 V is established to validate the feasibility of the proposed topology.

To address the rigorous demands of next-generation Wi-Fi MU-MIMO systems characterized by ultra-wide bandwidths, this paper presents a high-efficiency unified matrix processor tailored for Wi-Fi station devices. By leveraging a reconfigurable parallel-pipelined architecture and a novel low-complexity implicit eigenvalue decomposition (EVD) algorithm designed for beamforming feedback, the proposed design efficiently integrates multiple MU-MIMO tasks, including MIMO detection, precoding, and beamforming feedback, within a single core. This unified approach eliminates hardware redundancy inherent in traditional discrete implementations. Implementation results in 28 nm CMOS technology show that the proposed processor requires only 140 kGE at 320 MHz. Furthermore, with a high throughput of 160 MMatrices/s for beamforming feedback, the proposed architecture exhibits superior hardware efficiency, providing a scalable solution for high-performance Wi-Fi chips.

This paper proposes an analog-to-digital converters (ADC) calibration algorithm based on an AdaBoost-BP framework and a multi-dimensional-output network. By introducing an ensemble-learning strategy that enables collaborative decision-making across multiple network outputs, the proposed method achieves high-accuracy calibration while effectively avoiding convergence to local optima during training, thereby increasing the training success rate to 100%. The developed multi-dimensional-output calibration network significantly improves calibration throughput compared with existing calibration schemes based on multi-dimensional neural networks (MDNN). Experimental validation on a 14-bit commercial pipeline ADC demonstrates that, with clear improvements in both training success rate and calibration speed, at a sampling rate of 1 Gsps the post-calibration SNDR increases from 62.14 dB to 73.76 dB, and the SFDR improves from 77.11 dB to 92.57 dB.

This paper presents a broadband power amplifier (PA) for K/Ka-band applications. The PA is designed using a 0.7 μm InP DHBT process and employs a pre-matched cascode structure to enhance the breakdown voltage capability. By leveraging the even-order harmonic cancellation effect of a differential cascode topology combined with high-coupling on-chip transformer baluns, ultra-wideband impedance matching is achieved. The chip operates from 18 to 40 GHz with a compact size of 1.2 mm × 2.2 mm. Measurement results demonstrate a saturated output power of 21 dBm and a power-added efficiency (PAE) ranging from 26.5% to 37.8%. This design provides an effective solution for broadband PAs in K/Ka-band applications.

In recent years, permanent magnet vernier machines (PMVMs) have been studied by researchers because of their high torque density. The dual permanent magnet excited (DPME) machine, with permanent magnets in both the stator and rotor often exhibits a higher torque density than conventional single-side PMVMs. Due to the additional auxiliary permanent magnets on both sides, the torque ripple is also relatively high. And the variation relationships between the leading working harmonics and key parameters are diverse, which exists a certain extent of design conflicts in the process of optimization design. In this paper, in order to improve motor output torque and reduce torque ripple simultaneously, a split-tooth DPME machine with non-uniformly distributed stator teeth is proposed and designed purposefully.

This letter presents an inductorless wideband low-noise amplifier for broadband weak-signal readout front-ends. To achieve broadband input matching and low-noise operation without using inductors, the proposed architecture combines a g_m-boosted common-gate input stage with a feedforward noise-canceling path. A fully differential gain stage and a voltage-combining output buffer are also employed to support differential back-end processing and provide sufficient overall gain. The prototype is implemented in 65-nm CMOS with a 1-V supply, consuming 9.6 mW and occupying a core area of 0.044 mm². Measurement results show a peak gain of 32.5 dB with a −3 dB bandwidth of 0.4–2.2 GHz and a noise figure of 2.6–3.1 dB.

This paper presents high data rate wireless communications using ultra-wideband multicarrier (MC) transmission in the sub-terahertz band. An MC system operating in the 140 GHz band was developed and evaluated in outdoor LOS and NLOS environments. In the NLOS case, a reflector was designed based on the first Fresnel zone while accounting for incident-angle dependence. The system employs polarization division multiplexing to transmit two ultra-wideband signals. Experiments over a 50-m link achieved EVM values of approximately −22 dB in both environments, suggesting the feasibility of 50-Gbps transmission per polarization and 100-Gbps polarization-multiplexed transmission.

AI and edge-computing applications drive NAND Flash storage toward higher capacity and performance, but cross-temperature operation shifts threshold-voltage distributions (TVD) and degrades reliability and read performance. We construct a chip-level cross-temperature TVD shift model with on-chip temperature compensation circuit disabled and short-term retention loss suppressed. Based on this model, a read-reference-voltage compensation method, MB-RRVC, predicts read-voltage offsets from cross-temperature amplitude, program/erase (P/E) cycles, states, and layer positions. Experiments show that the method significantly reduces raw bit error rate (RBER) from 24.28% to 0.44% under extreme cross-temperature conditions, and SSDsim evaluation confirms a 43.81% reduction in average read response time.

This letter proposed a fully tunable Ultra High Frequency (UHF) microstrip diplexer based on convex resonant units with independent dual-channel frequency and bandwidth tuning. In this design, the matching function was integrated into the resonators without additional matching circuits. To verify the effectiveness of the design, a microstrip diplexer was designed, simulated and measured. The measured results showed the tuning range of 557–630 MHz in lower band and 820–920 MHz in upper band. The return loss was better than 15 dB and the channel isolation was better than 35 dB.

This letter addresses the difficulty of maintaining sufficient commutation-current margin near the grid-voltage zero crossings while limiting current stress over the remaining line cycle in a dual-active-bridge microinverter. A line-cycle-partitioned multimode modulation strategy is proposed. Explicit primary- and secondary-side commutation-current constraints are imposed in the low-instantaneous-power region, whereas mode-dependent local minimum-peak-current relationships are adopted elsewhere. An SPS-based hysteresis transition and offline-derived duty-ratio relationships avoid iterative online optimization. Experimental results from a 500 W prototype confirm the implementation of the four operating modes and representative ZVS turn-on. At 500 W, the secondary-current peak, grid-current THD, and efficiency are 8.13 A, 3.3%, and 96.1%, respectively; the maximum efficiency is 96.8% at 300 W.

This letter presents a discrete-time (DT) 3^rd-order ΔΣ ADC with a 4-bit noise-shaping SAR (NS-SAR) quantizer. A parallel-body-biased floating inverter amplifier is proposed, achieving competitive noise performance. In addition, a low-power floating flipped voltage follower (FFVF) is proposed for the NS-SAR quantizer, reducing power consumption by 22% compared to a conventional dynamic FVF design. Fabricated in a 65-nm CMOS technology, the prototype DT ΔΣ ADC achieves an SNR of 92.9 dB, an SNDR of 92.5 dB, an SFDR of 113.4 dB, and a DR of 93.2 dB with 100 kHz BW, while consuming 127.8 µW at a sampling rate of 10 MHz. This corresponds to an SNDR-based Schreier FoM of 181.4 dB and a DR-based Schreier FoM of 182.1 dB.

This paper presents a wide-load-range, high-frequency, high power-supply rejection (PSR) output-capacitorless low-dropout regulator (OCL-LDO) for high-speed optical communication chips. It proposes a load-current-adaptive negative capacitance (NCC) compensation technique to overcome the difficulty of maintaining high-frequency PSR enhancement over a wide load range. By sensing load current and tuning the feedback network, the adaptive negative capacitance (ANCC) circuit dynamically scales the amplifier gain and equivalent negative capacitance, compensating pass-transistor gate parasitics and supply-ripple coupling. Implemented in 0.18 μm CMOS, post-layout simulations show 0.1–50 mA operation. For loads above 10 mA, PSR remains below −67 dB at 100 kHz and −45 dB at 1 MHz, reaching −74 dB and −88 dB at 50 mA.