A 16-bit 210 MSPS pipelined analog-to-digital converter (ADC) with distributed differential reference voltage buffer (DDRVB) and foreground calibration is presented. Current summing and floating current control techniques are used in DDRVB to achieve high precision adjustable reference voltage. In order to improve the power supply rejection ratio (PSRR) and reduce the output impedance and power consumption, the push pull output and replica circuit structure is introduced. A mix-signal foreground calibration method for pipelined ADC is proposed. Offset, gain and mismatch errors in pipelined sub-stage circuits can be compensated by the proposed calibration method. Based on the proposed DDRVB and calibration method, a prototype 16-bit 210 MS/s pipelined ADC is designed and realized in a 1P6M 0.18 μm CMOS process. Test results show, the 16-bit 210 MSPS ADC core achieves the signal-to-noise ratio (SNR) of 77.3 dB and spurious free dynamic range (SFDR) of 101.7 dB, with 5.1 MHz input at full sampling speed, while consumes the power consumption of 495 mW.

This paper proposes a wide-range, energy-efficient differential cascade voltage switch (DCVS) Level-Shifter (LS), incorporating a cross-coupled pull-down auxiliary network to balance contention. It aims to provide a solution of contention problem in DCVS and improve its limited voltage conversion range. By comprehensively utilizing current-limiter, split-inverter, and multi-threshold transistor technology, the voltage conversion range is further expanded, and power consumption is reduced. In this design, the NMOS network is configured as a super-cut-off state during static conditions, significantly decreasing leakage power. The design is implemented based on 55 nm process. Post-simulation indicates that at a frequency of 1 MHz, the transmission energy is only 19.97 fJ (0.3 V-1.2 V), minimum voltage is 0.15 V. The leakage power is extremely low, at only 117.4 pW (0.3 V-1.2 V). Five LSs designed with similar processes were also re-implemented with 55 nm technology, and post-simulation shows that our design exhibits the lowest leakage power and transmission energy. Comprehensive comparison with others also proves that proposed design has reached the advanced level.

In digital systems, optimising the power and delay of flip-flops (FFs) can remarkably enhance its performance. In this paper, an ultra-low power flip-flop (CPCDFF) based on sense amplifier is proposed. The conditional pre-charge (CP) circuit achieves non-redundant transition, which enables power wastage to be reduced. A lite-latch structure is proposed to effectively reduced the CK-to-Q delay of the FF. The proposed completion detection (CD) technique effectively improves the reliability of the FF at near-threshold voltage. The proposed FF is implemented in 22 nm process, and a comprehensive analysis. At 0.8 V supply voltage, the post-layout simulation results show that the power of the proposed FF is only 0.151 μW@500 MHz and 10% data toggle rate; the power delay product is only 1.473 nW*ns@20 MHz at 20% data toggle rate. The Monte-Carlo simulation results considering the process, voltage, and temperature (PVT) variations indicated that the proposed FF could operate reliably down to a supply voltage of 0.4 V.

Failsafe radio-frequency (RF) switch module is an important kind of RF device, but cannot transmit high RF powers due to its significant direct-current (DC) dissipation. This letter presents an effective way to improve its RF power transmission capability by adopting the latching switch to transmit high RF powers and developing a conversion circuit in the front of the latching switch to enable the module to be failsafe. It has been found that at the frequencies of 1 GHz, 8 GHz, and 18 GHz, this module can respectively transmit RF powers as high as 140 W, 50 W, and 25 W on the ground and 100 W, 45 W, and 20 W at the altitude of 10000 m. This novel failsafe switch module is expected to be better applied to high-power-transmission scenarios.

Traditional RFID technology due to multiple tags concurrent responses lead to the sorting disorder, resulting in the accuracy of its logistics sorting system is difficult to break through the bottleneck of 0.01% -0.1%. This work proposes an innovative solution using light-activated tags and an integrated adaptive optical detection system with ambient light suppression. Compatible with standard RFID, its core innovation enables spatially unique, precise optical activation of target tags, eliminating identification errors from concurrent responses. Tape-out verification of ambient light adaptive optical sensing chip based on TSMC 180 nm CMOS process. This provides a practical, virtually error-free solution for high-value applications like airport logistics.

Integral nonlinearity (INL) is a key parameter of high-precision incremental sigma-delta analog-to-digital converters (ADCs). Spikes in measured INL plots have been encountered at specific points from reported studies, which however, are often ignored. Here, we report that the parasitic capacitance introduced by the reset switch in the auto-zero integrator in incremental ADC leads to output errors and visible spikes in the INL plot. We demonstrate the impact of this phenomenon through simulations and propose a compensation method by introducing symmetrical parasitic capacitance to counteract its effects. The design and improvement are further experimentally verified based on 0.25-μm CMOS process. An extended counting ADC based on incremental ADC with the parasitic capacitance demonstrates an INL of -4.13/+3.27 LSB, while the ADC with added symmetrical parasitic capacitance exhibits smaller spikes and lower INL of -2.14/+2.52 LSB.

A two-tap pinned photodiode (PPD) pixel using standard CMOS processes for high-speed time-of-flight (ToF) sensors is proposed in this paper. The buried n-well of this PPD can be realized by only one ion implantation, which effectively reduces the process complexity and realization difficulty of the PPD. TCAD simulation results verify that this PPD, based on a special shape design, generates a stable lateral charge transfer electric field when different taps are opened, which greatly improves the charge transfer speed and efficiency, i.e., the demodulation contrast of the pixel at high frequency can be effectively improved. Simulation results show that this PPD pixel achieves 83.5% demodulation contrast at a frequency of 50 MHz and 74.6% demodulation contrast at a frequency of 100 MHz, which can be applied to high-speed ToF sensors to effectively improve the depth measurement accuracy of the sensors.