This article aims to address how to study unidirectional radiation of a printed antenna using characteristic mode analysis (CMA). Two designs are used for the study and analysis. Firstly, the modal analysis of the radiator of the antenna is studied in omnidirectional state when the unidirectional technique has not been employed. Secondly, the unidirectional technique which involves using a shorted radiator-ground and a parasitic conductor is also employed its modal analysis is again studied. The modal currents show more uniform distribution for the omnidirectional antenna but for directional antenna, it exhibits high coupling currents in one single direction which indicates that a high gain end-fire radiation pattern can be realized. A simple microstrip feedline is used to excite the significant modes and end-fire radiation is indeed achieved through excitation. The presented antenna has an S₁₁ bandwidth of 2.3-6.4 GHz (94.5%), high front to back ratio across the bandwidth, and high peak gain of 10 dBi.

This paper proposes a Reverse Conducting Base Resistance-controlled Thyristor with P-body region (P-RC-BRT), which has high dV/dt immunity and achieves blocking at zero gate voltage. The characteristics of P-RC-BRT were compared with the conventional BRT and RC-BRT, and the pulse discharge characteristics of devices with different circuit parameters were analyzed, which were as high as 6208 A and 130.8 kA/μs. The dV/dt immunity of the devices was studied comparatively, the P-RC-BRT has higher dV/dt immunity.

Wireless charging systems have become increasingly popular, but they still suffer from standby power consumption even after batteries are fully charged. Recently, CPT wireless power transmission technology has been adopted. However, it can cause voltage spikes to damage the components when the battery is moved after complete charging. To address these issues, a low-cost circuit is proposed to eliminate standby power consumption. A microcontroller unit is used to control the switch of the power source. When the battery is fully charged, the switch will be turned off. Therefore, zero standby power consumption can be achieved by cutting off the power source from both the main circuit and the standby power reduction circuit. Experimental results show that the proposed circuit effectively eliminates standby power consumption while maintaining charging efficiency. This circuit can be easily implemented in wireless charging systems and can help improve energy efficiency and reduce power consumption.

Deep neural networks (DNNs) have achieved remarkable success in critical domains such as computer vision. However, their substantial model scale and computational demands hinder deployment on resource-constrained edge devices. Bit-serial accelerators (BSAs) leverage significant bit-level sparsity (BLS) in weights and activations to accelerate inference. Unstructured BLS causes hardware inefficiency, while existing static pruning methods cannot adapt to real-time activations. To address these challenges, we propose BitFleX, a BSA enabling runtime semi-structured pruning for both weights and activations. Specifically, we introduce Bit-Term Decomposition (BTD) encoding to enhance inherent BLS and reduce pruning complexity. Additionally, a pruning-error predictor dynamically selects operands for sparsification with minimal error. Experiments show BitFleX achieves 87.5% BLS in ViT-B with <1% Top-1 accuracy loss on ImageNet, yielding 5.86× speedup over baseline and 23.61 TOPS/W peak energy efficiency.

A multi-parameter tunable filter based on different U-type resonators was proposed in this letter. Through the introducing of back-to-back U-type resonator between two typical U-type resonators, the source/load cross coupling can be introduced between the input/output ports to improve the out of band suppression performance of the filter. Adopting of the structure, the center frequency and the cutoff frequency at the high-frequency end of the bandpass filter can be tuned and the one at low-frequency remains unchanged at the same time. A tunable filter with three resonators was designed, fabricated and measured. The simulated results were agreement well with the measured ones.

Complex ordinary differential equations (ODEs) are vital for scientific computations. This paper presents a Reconfigurable High-precision Complex ODE Solver (RHCOS) on FPGA with high area-efficiency. The RHCOS efficiently integrates Runge-Kutta and Adams algorithm by reconstructing the recursive structures through unified computing units and dynamic coefficient switching. Additionally, a cyclic update cache mechanism is introduced to reduce memory accesses and latency. Experimental results show that, for solving six-degree-of-freedom spatial dynamics equations, the RHCOS achieves a 14.1× speedup over software solution at 200 MHz, with high area-efficiency and an order of 10^-6 for relative computational error.

To suppress the turn-on of the parasitic body diode in SiC MOSFET, researchers have proposed various solutions. Among them, in this paper, a novel asymmetric SiC trench MOSFET with embedded N-base super barrier rectifier (ATN-SBR-MOS) is proposed and investigated. Benefiting from the lower threshold voltage of the SBR, the turn-on voltage (V_F) is reduced by 63%, thus the bipolar degradation issue is effectively eliminated. Moreover, the gate charge (Q_G) and reverse recovery charge (Q_RR) are shrunk by 59% and 36% respectively. Both of the switching characteristic are effectively improved,demonstrating significant potential for implementation in power device applications.

This paper presents an 8-bit 1-GHz single-channel successive approximation register (SAR) analog-to-digital converter (ADC) targeting ultra-high-speed wireline systems. The proposed design features a charge-sharing sampling technique with halved sampling time constant that accelerates quantization speed, and a novel embedded auto-zero comparator eliminating offset with minimal overhead. Fabricated in 28-nm CMOS technology and operating at 1-V supply, the ADC achieves 48.51-dB signal-to-noise-and-distortion ratio (SNDR) and 63.46-dB spurious-free dynamic range (SFDR) at a 1-GHz sampling rate while consuming 3.66 mW. Occupying only 0.0061 mm² core area, it demonstrates a figure-of-merit (FoMw) of 16.74 fJ/conv.-step(post-layout).

As an emerging nonlinear device, the piezoelectric memristor demonstrates significant potential in neuromorphic hardware and adaptive systems due to its unique electromechanical coupling and memory properties. However, its design and fabrication remain highly challenging, placing stringent demands on material selection and micro-nano processing techniques. Moreover, experimental studies based on physical devices are often costly, time-consuming, and inefficient for rapidly validating circuit-level application concepts. This paper proposes a novel circuit-based modeling approach that leverages the high sensitivity of piezoelectric sensors to mechanical stimuli, efficiently converting ambient mechanical energy into electrical signals. By integrating a Microcontroller Unit (MCU) with robust computational and real-time control capabilities, the circuit parameters can be dynamically adjusted to achieve precise modulation of memristance. This modeling strategy significantly reduces reliance on complex physical fabrication processes and offers researchers an efficient and low-cost platform for design and validation.

A fully tunable filter based on a novel non-uniform rectangular resonators was proposed in this letter. The center frequency and bandwidth can be adjusted independently through the tuning of the varactors loaded at the resonators. At the same time, a cross coupling structure can be easily introduced to improve the selectivity of the filters. In order to verify the effectiveness of the structure described in this letter, a third-order fully tunable filter adopting this structure was designed, simulated, fabricated, and measured. The measured results show that the bandwidth and frequency of the tunable filter can also be tuned. The insertion loss of this filter was better than 1.3 dB. The simulated results were in good agreement with the measured ones.

A compact filtering power divider with high performance and compact size is proposed. The filtering power divider is implemented using a half-mode substrate integrated waveguide (HMSIW) and loaded with the proposed strongly coupled complementary split-ring resonators (CSRRs). The proposed filtering power divider operates below the cutoff frequency of the waveguide. Firstly, the structure of HMSIW loaded with first-order CSRRs is analyzed, and the corresponding equivalent circuit is presented for the first time to facilitate analysis. Based on the first-order CSRR structure, a second-order CSRR structure is innovatively proposed, and its electric field distribution is analyzed. On this basis, filtering power dividers with equal power division and unequal power division are realized through cascading. The center frequencies of the two passbands can be adjusted by changing the dimensions of the CSRR structure and the central metal microstrip structure. To verify the proposed concept, a filtering power divider with equal power division is designed, fabricated, and tested. The measured results are in good agreement with the simulated ones. The proposed filtering power divider features compact size, dual-band operation, and good return loss.

This paper proposed an electrically small, high-efficiency, dual-band Huygens rectenna for microwave wireless power transfer (MWPT), which innovatively combined a bandwidth-enhanced electrically small dual-band Huygens antenna with a highly efficient rectifier. The antenna consists of two sets of near-field resonant parasitic (NFRP) elements with identical geometry but different dimensions. The antenna achieves electrically small (ka = 0.91@0.9 GHz) and low profile (0.02 λ₀). A λ/4 dual-band coupler is employed to accomplish impedance matching between the dual-band Huygens antenna and the high-efficiency rectifier, thereby combining them into an electrically small, highly efficient dual-band rectenna. The proposed rectenna achieves peak power conversion efficiency (PCE) of 74.4% at 0.9 GHz and 63.9% at 2.5 GHz over a wide input power range from -3 dBm to 30 dBm. Overcoming the application limitations of previous single-band Huygens rectennas, this work provided a compact and high-efficiency solution for MWPT.

This paper introduces a novel area-efficient asymmetric butterfly (AsymFly) network-on-chip (NoC) architecture, specifically designed to manage the communication-intensive traffic patterns generated by large language models (LLMs) on GPGPUs. The proposed architecture strategically places memory and compute nodes on opposite sides of the network fabric. This physical arrangement, combined with node consolidation, reduces the router count by 17%. Furthermore, we employ pipeline-stage time-division multiplexing (TDM) to enhance resource utilization and achieve protocol-level deadlock avoidance within a unified physical network. To counteract throughput degradation induced by TDM, we propose a local adaptive scheduling strategy that dynamically balances resource occupancy across network regions. Compared to a conventional mesh baseline, our evaluations demonstrate that AsymFly improves instructions per cycle (IPC) by 26% while reducing both area and power consumption by 64%.

This study proposes a dynamic guided spontaneous-emission circuit (DGSEC) technique that achieves significantly enhanced signal-to-noise ratios (SNRs) for optical power variation measurement. The output power (P_out), time constant (τ), slope (S), and SNR enhancement factor (ΔSNR) of the DGSEC are experimentally investigated and clarified for the first time. Experimental results confirm that an increase in P_out leads to a decrease in τ (advantage) and decreases in S and ΔSNR (drawbacks), thereby establishing trade-off relationships among the four parameters. A remote sensing experiment over a 15-km single-mode fiber demonstrates successful operation of an optimized DGSEC with a ΔSNR of approximately 22.5 dB.