IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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A counter-based all-digital spread-spectrum clock generator with high EMI reduction in 65nm CMOS
Ching-Che ChungDuo ShengWei-Da Ho
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Keywords: EMI reduction, ADPLL, SSCG
JOURNALS FREE ACCESS

2013 Volume 10 Issue 6 Pages 20130090

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Abstract

An all-digital spread-spectrum clock generator (ADSSCG) with direct modulation on the digitally controlled oscillator (DCO) is presented. The proposed ADSSCG can generate an accurate triangular modulation on the output frequency, and thus it can achieve high electromagnetic interference (EMI) reduction with a smaller spreading ratio as compared with existing designs. In addition, the proposed frequency counter-based mechanism can maintain the long-term frequency stability of the ADSSCG. The proposed ADSSCG is implemented in a standard performance 65nm CMOS process, the active area is 85μm × 85μm. It consumes 163.9μW at 270MHz with a 1.0V power supply. The EMI reduction of the proposed ADSSCG is 13.99dB with a 0.5% spreading ratio at 270MHz, and 20.23dB EMI reduction is achieved with a 1.5% spreading ratio at 162MHz. Moreover, the proposed ADSSCG is designed with standard cells, and thus it can be ported to different process in a short time.

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© 2013 by The Institute of Electronics, Information and Communication Engineers
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