Abstract
A self-correcting check bit generator (SCO-CBG) is proposed that can correct errors in the check bits produced by faulty check bit generator (CBG). The SCO-CBG amends check bit errors using the concept of error correction code (ECC) techniques. In the SCO-CBG, the parity bits and predicted parity bits function as the check bits of the ECC techniques. The SCO-CBG and the conventional triple modular redundancy (TMR) CBG are implemented using 45nm library. When compared with the TMR CBG, the SCO-CBG reduces the area overhead and power consumption for 128 data bit word by up to 48.4% and 47.0%, respectively.
