Linearity enhancement technique of ramp generator for ADC testing

Abstract

This work presents the method to enhance the linearity of ramp generator for ADC testing. Through utilizing the parasitic model of capacitance, we develop an extraction method to estimate parasitic components concerning with linearity of integration for ramp generator. The further use of negative impedance converter provides adjustable negative impedance for compensating redundant parasitic components. The resulted impedance is almost pure capacitance enabling the possibility of very linear current integration for ramp generator. The simulation results show that the proposed method is able to generate very linear ramp signal for constant current source. The differential and integral nonlinearity of ramp signal is almost reduced to one-twentieth of that without compensating.