抄録
Complementary Metal-Oxide-Semiconductor (CMOS) process and silicon device technologies have progressed dramatically in the last ∼50 years. The achievements of semiconductor industry have dramatically improved the human lifestyle making it smarter. One of the biggest factors in this change is the continued CMOS scaling. However, at sub-30-nm CMOS technology nodes, one of the main technical barriers for reducing the size of CMOS silicon devices is the parametric failure caused by random variations such as line-edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). This paper discusses these issues in terms of (1) the physical understanding and quantitative evaluation of each random variation source, and (2) the technical solutions to address each of these random variation issues. Lastly, the silicon device scaling scenario from the past, the present and through to the future (i.e., 90 nm technology down to sub-10-nm technology) is briefly discussed.
