Reduced-error constant correction truncated multiplier

抄録

Constant correction truncated multiplier can minimize hardware cost and power dissipation by computing only the most significant bits of partial products. However, traditional schemes introduce large truncation errors that degenerate the accuracy of the target application. In this brief, we propose an improved scheme that can significantly reduce such truncation errors. The proposed scheme estimates an accurate compensating constant by correctly counting the probability of occurrence of the input operand and the product bits with a group of probability propagation formulas. The proposed truncated multiplier is coded in Verilog RTL, implemented in 65 nm standard cell technology, and applied in image compression and color space conversion applications. Experimental results show that our scheme achieves an average peak signal-to-noise ratio (PSNR) improvement of 4.09 dB and 2.31 dB over state-of-the-art truncation scheme in the two applications, respectively. When the same truncation error range is desired, the proposed scheme can save around 5.8% of circuit area.